SoM Overview to NVIDIA Jetson AGX Thor
 | The NVIDIA Jetson AGX Thor documentation from RidgeRun is presently being developed. |
SoM Overview
This section provides an overview of the Jetson AGX Thor SoM components and their capabilities.
The NVIDIA Jetson Thor establishes a new benchmark in embedded edge computing by delivering over 800 tera operations per second (TOPS) of AI performance while maintaining remarkable energy efficiency. The Jetson Thor System on Module (SoM) is a compact printed circuit board that integrates NVIDIA’s most advanced computing components, including next-generation Arm CPUs, an NVIDIA GPU based on the latest architecture with support for transformer engines, high-speed memory, and cutting-edge AI accelerators. In addition, the SoM provides essential subsystems such as high-bandwidth interfaces, networking, storage connectivity, and dedicated hardware engines for vision and sensor processing. This level of integration allows Jetson Thor to bring data center–class AI capabilities directly to autonomous machines, robotics platforms, and industrial edge devices. Figure 1 shows an image of the Jetson Thor dev kit.
Table 1 shows a summary of the hardware characteristics of the SoM:
| Feature | Jetson T5000 |
|---|---|
| AI Performance | 2070 FP4 TFLOPS / 1035 FP8 TFLOPS |
| GPU | NVIDIA Blackwell Architecture with 2560 NVIDIA® CUDA® Cores and 96 5th GEN Tensor Cores (3GPC), 10-TPCs MIG Support |
| Max GPU Freq | 1.575 GHz |
| CPU | 14x core Arm® Neoverse V3AE (64-bit) symmetric multi-processing (SMP) CPU architecture, L1 Cache (I, D) per core:
64KB + 64KB, L2 Cache per core: 1MB, L3 Cache 16MB shared System Cache, SPECint@2017_int_base (one core): 6.6, SPECrate@2017_int_base (all cores): 80 |
| CPU Max Freq | 2.6 GHz |
| Memory | 128GB LPDDR5x DRAM 4266 MHz 256-bit, 273 GB/s |
| Storage | External Storage (NVMe via PCIe and SSD via USB 3.2), 64MB NOR Boot Flash |
| Deep Learning Accelerator | Not Applicable |
| Vision Accelerator | PVA v3.0 |
| Encoder |
|
| Decoder |
|
| CSI Camera |
|
Graphic Features
Blackwell graphics deliver advanced rendering and compute features with full end-to-end lossless compression, tiled caching, and broad API support (OpenGL 4.6+, Vulkan 1.2+, CUDA 11.4+). They include:
- ASTC LDR texture compression
- Modern graphics techniques such as:
- Ray tracing
- DL inferencing
- Mesh shaders
- Sampler feedback
- Variable rate shading
- Compute-based texture LOD.
Additional enhancements include:
- 2D/3D texture support with FP16 filtering
- Multi-sample anti-aliasing (2x, 4x, 8x) with compression
- FP16 shader support
- Geometry and vertex instancing
- Parallel pixel processing
- Efficient early-Z rejection to save bandwidth and power.
The architecture also supports color compression, advanced blend modes, and video protection regions, enabling high performance, efficiency, and modern graphics functionality across a wide range of workloads.
Multi-Standard Encoder (NVENC)
The module integrates two NVIDIA Multi-Standard Video Decoders (NVDEC), enabling accelerated playback of content from SD up to 8K. Through a video DMA interface, it supports multiple memory output formats and uses dynamic frequency scaling for low-power, real-time operation. Supported codecs include:
- H.265/HEVC
- H.264
- VP9
- VP8
- AV1
- MPEG-4
- MPEG-2
- VC-1.
Multi-Standard Decoder (NVDEC)
The module integrates two NVIDIA Multi-Standard Video Encoders (NVENC), providing full hardware acceleration for high-quality H.265 (HEVC) and H.264 video encoding. Designed for mobile use cases such as video recording and conferencing, the encoders deliver strong performance with exceptional power efficiency. Supports:
- H.264
- H.265
Programmable Vision Accelerator
The Thor PVA is NVIDIA’s third-generation vision DSP, designed as a vector processor optimized for computer vision, VR/AR, and sensor processing tasks. It provides predictable low-latency performance at low power, offloading workloads from the GPU to extend battery life and thermal efficiency in robotics and embedded systems. A PVA cluster includes:
- Dual Vector Processing Units (VPUs) with VLIW instruction streams
- Dual 2D Pixel Processing Engines (PPEs)
- Decoupled lookup units (DLUTs)
- Dual DMA engines with tensor access
- 512 KB of local memory per VPU
- 1 MB of L2 SRAM
- Dedicated hardware scheduling.
Performance reaches up to 622 INT16 GMAC/s and 2488 INT8 GMAC/s on the VPUs, with up to 320 FP16 GFLOPs and 165 FP32 GFLOPs, while PPEs add 194 INT16 GMAC/s and 97 INT32 GMAC/s, making the PVA a powerful accelerator for vision and sensor workloads.
Optical Flow Accelerator
The Optical Flow Accelerator (OFA) is a hardware unit designed to compute optical flow and stereo disparity between frames. It operates in two modes:
- Stereo Disparity Mode: where it processes rectified stereo pairs to generate disparity values.
- Optical Flow Mode: where it calculates motion vectors between frames using a multi-level image pyramid.
The OFA produces block-wise outputs at grid sizes of 1×1, 2×2, or 4×4 pixels, which can be further processed or up sampled into dense maps. Both disparity and flow outputs are provided in fixed signed 10.5 format and must be divided by 32 to obtain values in pixel units. It supports a wide range of input sizes and bit depths while enabling efficient, low-power real-time operation.
Codecs
JPEG Codec (NVJPEG)
It consists of hardware engine with two instances of NVJPEG HW:
- 2x NVJPEG
- Performance: 2x 1500 MPix/Sec
Supports:
- Color space conversion: RGB to YUV
- YUV420, YUV422H/V, YUV444, YUV400 image scaling decoding
Central Processing Unit (CPU) Complex
The CPU cluster integrates 14 Arm Neoverse V3AE cores based on the Arm v9.2-A 64-bit architecture. Each core includes dual 128-bit NEON and dual 128-bit SVE2 engines, separate 64 KB instruction and data caches, and a unified 1 MB L2 cache. Key features include:
- SIMD and floating-point support
- Cryptographic acceleration
- Memory management
- Advanced debugging
- Profiling extensions
- Error detection
- CoreSight v3.0 support
- Power efficiency enabled through dynamic power gating.
The system also incorporates an external NVIDIA Hardware Performance Monitor (HWPM), which collects detailed runtime statistics on processor and memory behav
Video Input
This block receives data from the CSI receiver and prepares it for presentation to system memory or the dedicated image signal processor execution resources. The VI block provides formatting for RGB, YCbCr, and raw Bayer data in support of several camera user models. These models include single and multi-camera systems, which may have up to six active streams. The input streams are obtained from MIPI compliant CMOS sensor camera modules.
Image Signal Processor (ISP)
Jetson Thor integrates two Image Signal Processors (ISPs) capable of handling raw Bayer data from sensors or memory and converting it to YUV output. The imaging subsystem supports sensors up to 24 MP and applies advanced processing to correct artifacts from high-resolution CMOS sensors and optics. Each ISP runs at up to 1215 MHz, delivering 3.5 GPixel/s throughput. Key features include:
- Hardware noise reduction
- Black-level
- Lens shading compensation
- Bad pixel correction
- Color and gamma correction
- Tone mapping
- Improved de-mosaic algorithms
- HDR support up to 20-bit dynamic range
- Flexible architecture for custom computer vision and computational imaging tasks.
Video Image Compositor (VIC)
The VIC is a power-efficient engine for 2D image and video processing, supporting:
- UI rendering
- Video playback post-processing
- Camera capture enhancements
It provides HDR and pixel format processing, scaling, color conversion, blending, rotation, and memory format conversion.
Its advanced noise reduction capabilities include:
- Bilateral spatial filtering
- Motion-adaptive temporal noise reduction
- Programmable coefficients for flexible tuning.
The VIC also features geometry transform processing with real-time warp map generation, enabling correction of optical distortions and perspective adjustments, making it well-suited for wide FOV and immersive imaging applications.
Dual Audio and Sensor Processing
The Always-On (AON) cluster integrates a Cadence Xtensa F1 DSP (Tensilica LX7) with a DSP co-processor for audio and sensor processing. It is designed for low-power sensor management and wake functions, and includes internal DMA, control fabric, low-speed I/O, and other IPs. The Xtensa F1 implementation features Armv7-R ISA, instruction and data caches, tightly coupled memory, vectored interrupts, and multiple AXI/AHB interfaces for DRAM, MMIO, and local SRAM access, ensuring efficient low-latency processing in always-on scenarios.
High Definition Audio Subsystem
uses a collection of functional blocks to off-load audio processing activities from the CPU complex, resulting in fast, fully concurrent, and highly efficient operation.
Audio Processing Engine (APE)
APE in the SoC can perform audio processing with minimal supervision from the main CPUs if required. It can also split audio processing tasks with the main CPUs, in which case the APE is generally used for more latency
critical processes.
The APE contains an Audio DSP cluster (ADSP), an Audio Hub (AHUB) equipped with
multiple hardware accelerators for audio signal pre-processing and post-processing, and
an Audio DMA engine (ADMA).
High Definition Audio (HDA)
Jetson Thor integrates a High-Definition Audio (HDA) controller that delivers multi-channel audio over HDMI and DisplayPort, while also supporting an HDA-compliant serial interface to external codecs. It can handle up to four audio streams, stripe output across multiple SDO lines, and operate with DVFS for low-latency audio. Supported formats include uncompressed LPCM (16/20/24-bit, up to 192 kHz) and a wide range of compressed standards such as AC3, DTS, MP3, AAC, TrueHD, and DTS-HD.
Power and System Management
Table 2 shows the power and system characteristics of the AGX Thor.
| Feature | Description |
|---|---|
| Input Power | Supports three main inputs: SYS_VIN_HV (7–20V), SYS_VIN_MV (5V), SYS_VIN_SV (3.3V), plus PMIC_BBATT (1.85–5.5V) for RTC backup. Power is regulated and sequenced by onboard ICs; carrier board must supply inputs. |
| Power Rails | All module voltages and I/O are derived internally from the supplied rails; no external I/O voltage required. |
| Power Domains / Monitoring | Single 3-channel INA measures power consumption on main inputs. |
| Power Management Controller (PMC) | Manages transitions between performance and low-power modes, supports aggressive power gating, and handles wake events (SPI, I2C, RTC, USB). |
| Power States | Three modes: ON (full operation), OFF (default when unpowered or after shutdown/thermal event), and SLEEP (low-power, fast resume, includes SC7 deep sleep). |
| Reset Mechanism | Resets SoC and storage; used in power sequencing. Includes SYS_RESET_N, PERIPHERAL_RESET_N, and FORCE_RECOVERY_N for system recovery/debug. |
| PMIC_BBATT (RTC Backup) | Optional backup battery input (1.85–5.5V) to maintain real-time clock when VIN is absent. Consumption: 12–50 μA. No recharge supported. Accuracy: ±10s/day. |
| Power Sequencing | Module must power up before carrier board circuits. Correct sequencing is required to avoid damage. |
| Thermal & Power Monitoring | Integrated hardware/software thermal management with throttling and external thermal alerts. Designed for active or passive cooling solutions. |
Interface Description
Table 3 shows the interface description characteristics of the AGX Thor SoM
| Features | Description |
|---|---|
| MIPI CSI (NVCSI 2.0 + VI 6.0) | Supports MIPI CSI-3.0, D-PHY v2.1 (40 Gbps) and C-PHY v2.1 (164 Gbps). Up to 16 virtual channels per ISP, data type interleaving, 6 pixel parsers, and high-throughput parallel pixel processing. |
| Camera over Ethernet (CoE) | Enables image data transfer over Ethernet networks, reducing cabling by sharing existing infrastructure instead of point-to-point links. |
| USB (XUSB Controller) | USB 3.2 Gen1/Gen2 and USB 2.0 supported. Host & Device (limited). Supports low-power states, remote wake, 10 Gbps (shared on ports 0/1), and full USB link power management. |
| PCI Express (PCIe Gen5) | 5 controllers, flexible configs (x1, x2, x4, x8). Supports up to 32 Gbps per lane, total of 144 GT/s. Supports Root Port and Endpoint modes. |
| SPI | Duplex, synchronous serial communication. Supports initiator/target, multiple modes, 4–32 bit packet sizes, Tx/Rx FIFOs, up to 67.5 MHz (initiator), 45 MHz (target). |
| QSPI | Two controllers (boot + secure key). Supports SDR/DDR, single/dual/quad modes (boot only). 64×32-bit FIFOs, DMA support, write/read sequences. Only 1.8V flash devices. |
| UART | 4 controllers, up to 4.25 Mbps, DMA for TX/RX, parity & error detection, FIFO buffers, modem control, auto baud detection, flow control. Requires 2 stop bits for reliable sync. |
| CAN | Supports CAN 2.0A/B and CAN FD (ISO & Bosch formats). Up to 4 buses, bit rates up to 8 Mbps, TTCAN Level 0–2, message filtering, watchdog timer, and loopback mode. |
| I2C | 13 controllers. Supports Standard (100 kbps), Fast (400 kbps), Fast+ (1 Mbps). Master and slave modes. Clock/speed negotiation. |
| I2S / Audio Interfaces | Supports I2S, PCM, DSP, RJM, LJM modes. Full/half duplex. Up to 49.152 MHz in TDM/PCM. Supports telephony mode, TDM with flexible slots, and flow control. |
| Ethernet (MGBE) | 4x Multi-Gigabit Ethernet controllers, up to 25 Gbps each (100 Gbps aggregate). Supports IEEE 802.3-2015, TSN, AVB, VLANs, and Precision Timing Protocol. |
| PWM | Programmable pulse-width modulation with frequency from 27 MHz or 202.5 MHz sources. Controlled by 8-bit duty cycle register. |
| JTAG | Debugging interface, up to 15 MHz clock. |
Pin definitions
Each Jetson Thor pin is assigned as either a Special-Function I/O (SFIO) or a General-Purpose I/O (GPIO), configurable through software. GPIOs can function as input, output, or interrupt sources with full edge/level control. This flexibility is managed via Multi-Purpose I/O (MPIO) pads, which integrate output drivers (push-pull/open-drain with drive strength and tristate), input receivers (Schmitt or CMOS), and weak pull-ups/pull-downs. These pads are grouped into “pad control groups,” controlled by the pinmux registers during operation.
Table 4 shows the pin description characteristics of the AGX Thor SoM
| Feature | Description |
|---|---|
| Power-On Reset (PoR) Behavior | Each pad has a defined reset state to minimize external components. For instance, weak pull-ups are enabled for active-low chip selects by default. Boot flow: system hardware powers up → releases SYS_RESET_N → Boot ROM initializes I/O controllers → fetches Boot Configuration Table (BCT) + bootloader → if successful, passes control to bootloader; if not, enters USB recovery mode. |
| Sleep Behavior (DPD) | In Sleep/Deep Sleep, most pads enter Deep Power Down (DPD). Input buffers may be disabled, enabled as GPIO wake events, or reserved for special functions. Output buffers may hold static values or remain dynamic, while weak pull-ups/pull-downs can be disabled or configured. Certain critical pads remain active during deep sleep. |
| GPIO | Jetson Thor provides multiple dedicated GPIOs, each configurable as input, output, or interrupt with full edge/level control. All eligible pins expose GPIO functionality via the Pinmux. |
| B2B Connector Pinout | The module uses a 699-pin board-to-board connector. A simplified pinout is included in the design guide, with full details available in the pin description spreadsheet provided with the Jetson Thor Design Guide. |
Known Issues
| Issue | Description |
|---|---|
| 5383804 | Flashing of FPGA FW might fail if setup is not properly configured.
To prevent FPGA FW failure, ensure the following steps are followed:
the type of camera you are using, per the user guide instructions.
|
| 5454877 | The nvsipl_coe_camera application fails to run inside a Docker container. Use
the following workaround to fix the problem.
In the file
lib, /usr/lib/nvsipl_uddf/libnvuddf_eagle_library.so lib, /usr/lib/nvsipl_drv/libnvsipl_qry_vb1940.so lib, /var/nvidia/nvcam/settings/sipl/vb1940.nito |
| 5456784 | Using Jetson IO to configure Jetson Camera Hawk-Owl p3762 module could
sometimes lead to the display being stuck. |
| 5445933 5472056 5446087 |
Intermittent failures could be observed when pinging cameras over Ethernet.
When running SIPL example applications, random I2C errors and capture failures are seen because of UDDF driver header incompatibility. Apply the following WAR to help fix the issues:
|
| 5461056 5398396 |
Argus crash can be seen while running preview/capture use cases for
E3333[OV5693], E3331[IMX318], or IMX185, due to the opening sequence of streaming only. Use override.cfg files for the sensors to avoid this issue. |
| 5436810 | CUDA BL memory is not supported for encode and decode use cases. |
| 5451745 | De-interlace decode is not supported. |
| 5437529 | Slice-level encoding is not supported. |
| 5236938 | Init time delay for multi-instance decode use cases. |
| 5452012 | GStreamer nvsiplsrc plug-in requires nvvidconv to copy the buffers because
it does not work directly with the encoder. |
| 5216744 | GStreamer nvv4l2decoder plug-in does not support JPEG/MJPEG decoding. |
| 5388059 | USB camera preview fails with OSS Cheese application due to conflicts
between OSS and NVIDIA JPEG library. |
| 5416070 | DVFS is not fully optimal for multimedia use cases |
| 4506985 | The emc_log tool is not showing correct memory bandwidth for iGPU-based
NVJPG HW engine on Jetson Thor. |
| 5466051 | The NVIDIA FFMPEG HW acceleration is currently not supported on Jetson
Thor. If your applications require FFMPEG, you can use the open source version with the following steps: sudo apt-get install -y ffmpeg |
| 5451920 | GStreamer nv3dsink plug-in hangs in DRC use cases. |
| 5440020 | Bluetooth re-connections for LE keyboard and mice do not work on the initial
pair. They will work after device reboot or Bluetooth reboot or toggling the connected device from settings page. |
| 5226667 5465140 |
Wi-Fi 6-GHz routers that use MBSSID are not supported. |
| 5426982 | Sometimes in a busy environment, not all Wi-Fi access points are observed
due to limited buffer size for scan results. |
| 5424504 | UEFI menu is slow to respond during ISO installation on some 4K monitors.
This issue does not affect the functionality. |
| 5380828 | Toggling fractional scaling options in display settings on desktop could lead to
some flickering on the background. |
| 5437402 | When two displays are connected to target one over HDMI and another over
DP, the NVIDIA logo gets clipped during boot up and reboot. |
| 5422032 | In a dual-monitor setup, enabling desktop scaling may cause window
corruption or visual artifacts |
| 5378590 | Changing display orientation to Landscape Flipped or Portrait Right or Portrait
Left does not work. |
| 5092683 | Fisheye python samples fail to run because of OpenCV compatibility issues. To
work around this issue, install the following: sudo python3 -m pip install opencv-python==4.8.0.74; sudo python3 -m pip install pillow numpy==1.26; |
| 5228336 5462083 |
For details, refer to the VPI Release Note. |