V4L2 FPGA - Examples - Convolutioner

V4L2 FPGA
Introduction
Overview Frame Grabber Sink Filtering Budget Estimator
Getting the Code
How to get the code Building and Installation Guide Running the demo
Examples
Convolutioner Pass Through Video Test Pattern Generator Xilinx OpenCV
GStreamer Pipelines
Filter Mode Frame Grabber
Supported Platforms
PicoEVB Zynq 7000 series Zynq MP-SoC series LiteFury
Contact Us

This accelerator is capable of receiving a video frame from the kernel space, apply a Gaussian blurring through a convolution in space (custom kernel values are planned for future releases) and return the frame to the kernel. This operation allows reducing the noise on an image and correct minor errors.

With multiple convolution accelerators, it is possible to perform more complex operations, such as demosaicing, Sobel, DoG (Differential of Gaussian), LoG (Laplacian of Gaussian), and other spatial filters. The code of the accelerator will be available after purchasing V4L2-FPGA and you can modify the code in order to implement other types of filters or increase the kernel size.

Hardware description optimizations allow this accelerator to avoid any bottleneck created by this module, thanks to data parallelism, fitting up to eight pixels in a single bus transference.

That's not all! More optimizations are coming in our goal to achieve 30fps @4K.

• 

  Input solid line

• 

  Line after convolution