V4L2 FPGA/Examples/Convolutioner: Difference between revisions
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This accelerator is capable of receiving a video frame from the kernel, apply a | This accelerator is capable of receiving a video frame from the kernel space, apply a Gaussian blurring through a convolution in space (custom kernel values are planned for future releases) and return the frame to the kernel. This operation allows reducing the noise on an image and correct minor errors. | ||
With multiple convolution accelerators, it is possible to perform more complex operations, such as demosaicing, Sobel, DoG (Differential of Gaussian), LoG (Laplacian of Gaussian), and other spatial filters. The code of the accelerator will be available after purchasing V4L2-FPGA and you can modify the code in order to implement other types of filters or increase the kernel size. | |||
Hardware description optimizations allow this accelerator to avoid any bottleneck created by this module, thanks to data parallelism, fitting up to eight pixels in a single bus transference. | |||
That's not all! More optimizations are coming in our goal to achieve 30fps @4K. | |||
Revision as of 14:29, 18 July 2019
| V4L2 FPGA |
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| Introduction |
| Getting the Code |
| Examples |
| GStreamer Pipelines |
| Supported Platforms |
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This accelerator is capable of receiving a video frame from the kernel space, apply a Gaussian blurring through a convolution in space (custom kernel values are planned for future releases) and return the frame to the kernel. This operation allows reducing the noise on an image and correct minor errors.
With multiple convolution accelerators, it is possible to perform more complex operations, such as demosaicing, Sobel, DoG (Differential of Gaussian), LoG (Laplacian of Gaussian), and other spatial filters. The code of the accelerator will be available after purchasing V4L2-FPGA and you can modify the code in order to implement other types of filters or increase the kernel size.
Hardware description optimizations allow this accelerator to avoid any bottleneck created by this module, thanks to data parallelism, fitting up to eight pixels in a single bus transference.
That's not all! More optimizations are coming in our goal to achieve 30fps @4K.