IMX8/IMX6vsIMX8: Difference between revisions
< IMX8
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! scope="row" | Security | ! scope="row" | Security | ||
| style="text-align: left" | Secure Boot, RNG, Tamper Detection, secure storage, AES-128, DES 3DES, ARC4, MD5, SHA-1, SHA-224, SHA-256, 16KB Secure RAM, tamper-resistant RTC, secure debug, OTP Space || style="text-align: left" | <li>Resource Domain Controller (RDC) supports four domains and up to eight regions</li><li>Arm TrustZone (TZ) architecture</li><li>On-chip RAM (OCRAM) secure region protection using OCRAM controller</li><li>High Assurance Boot (HAB)</li><li>Cryptographic acceleration and assurance (CAAM) module</li><li>Secure non-volatile storage (SNVS): Secure real-time clock (RTC)</li><li>Secure JTAG controller (SJC)<li> | | style="text-align: left" | Secure Boot, RNG, Tamper Detection, secure storage, AES-128, DES 3DES, ARC4, MD5, SHA-1, SHA-224, SHA-256, 16KB Secure RAM, tamper-resistant RTC, secure debug, OTP Space || style="text-align: left" | <li>Resource Domain Controller (RDC) supports four domains and up to eight regions</li><li>Arm TrustZone (TZ) architecture</li><li>On-chip RAM (OCRAM) secure region protection using OCRAM controller</li><li>High Assurance Boot (HAB)</li><li>Cryptographic acceleration and assurance (CAAM) module</li><li>Secure non-volatile storage (SNVS): Secure real-time clock (RTC)</li><li>Secure JTAG controller (SJC)<li> | ||
|- | |||
! scope="row" | Timer | |||
| style="text-align: left" | 3 || style="text-align: left" | 3 | |||
|- | |||
! scope="row" | Real-Time Clock | |||
| style="text-align: left" | Secure RTC || style="text-align: left" | Secure RTC | |||
|- | |||
! scope="row" | Pulse Width Modulation | |||
| style="text-align: left" | 4 || style="text-align: left" | 4 | |||
|} | |} | ||
Revision as of 19:15, 8 November 2018
Features | i.MX6 Quad / i.MX6 Dual | i.MX8M Dual / i.MX8M QuadLite / i.MX8M Quad |
---|---|---|
CPU | ||
Maximum CPU Frequency | ||
I-Cache/D-Cache | 32 KB/32 KB L1, 1 MB L2 |
|
External Memory Interface | 2 x 32 LP-DDR2, 1-ch. x 64 DDR3/DDR3L | |
Display Interface | HDMI + PHY 2 x parallel, 2 x LVDS, MIPI DSI |
|
Hardware Video Acceleration | HD (1080 + 720)p30 video decode HD 1080p30 video encode |
|
Hardware 2D/3D Graphics Acceleration | ||
Camera Sensor Interface (CSI) | ||
Universal Asynchronous Receiver/Transmitter (UART) | 5 | 4 |
Serial Peripheral Interface (SPI)/I2C | 5/3 | 3/4 |
USB Controller | Each USB instance contains: USB 3.0 core, which can operate in both 3.0 and 2.0 mode | |
Power Management | ||
Digital Audio Interface | ||
Ethernet | ||
PCI Express | ||
Multimedia Card (eMMC)/Secure Digital Controller (SDIO) | 4 x eMMC 4.5 / SD 3.0 | 2x eMMC 5 / SD 3 NAND CTL (BCH62) |
Security | Secure Boot, RNG, Tamper Detection, secure storage, AES-128, DES 3DES, ARC4, MD5, SHA-1, SHA-224, SHA-256, 16KB Secure RAM, tamper-resistant RTC, secure debug, OTP Space | |
Timer | 3 | 3 |
Real-Time Clock | Secure RTC | Secure RTC |
Pulse Width Modulation | 4 | 4 |