IMX8/IMX6vsIMX8: Difference between revisions
< IMX8
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! scope="row" | I-Cache/D-Cache | ! scope="row" | I-Cache/D-Cache | ||
| style="text-align: center" | 32 KB/32 KB L1, 1 MB L2 || style="text-align: center" | | | style="text-align: center" | 32 KB/32 KB L1, 1 MB L2 || style="text-align: center" | '''Arm Cortex-A53:'''<br><li>32 KB L1 Instruction Cache<br></li><li>32 KB L1 Data Cache<br></li><li>Support L1 cache RAMs protection with parity/ECC<br></li>'''Arm Cortex-M4:'''<br><li>16 KB L1 Instruction Cache<br></li><li>16 KB L1 Data Cache<br></li><li>256 KB tightly coupled memory (TCM)</li><br> | ||
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! scope="row" | External Memory Interface | ! scope="row" | External Memory Interface | ||
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! scope="row" | Display Interface | ! scope="row" | Display Interface | ||
| style="text-align: center" | HDMI + PHY, 2 x parallel, 2 x LVDS, MIPI DSI || style="text-align: center" | HDMI Display Interface:<br> | | style="text-align: center" | HDMI + PHY, 2 x parallel, 2 x LVDS, MIPI DSI || style="text-align: center" | '''HDMI Display Interface:'''<br> | ||
<li>HDMI 2.0a (1 display): | <li>HDMI 2.0a (1 display): up to 4096x2160 @ 60 Hz,<br>support HDCP 2.2 and HDCP 1.4<br></li><li>20+ Audio interfaces 32-bit @ 384 kHz fs with Time Division Multiplexing (TDM) support<br></li><li>S/PDIF input and output<br></li><li>Audio Return Channel (ARC) on HDMI<br></li><li>Upscale HD graphics to 4K for display<br></li><li>Downscale 4K video to HD for display<br></li><li>Display Port<br></li><li>Embedded Display Port</li><br> | ||
< | '''MIPI-DSI Display Interface:'''<br><li>MIPI-DSI 4 channels supporting one display, up to 1920x1080 @ 60 Hz<br></li><li>LCDIF display controller<br></li><li>Output can be LCDIF output or DC display controller output</li><br> | ||
< | '''Audio:'''<br><li>S/PDIF input and output<br></li><li>Five synchronous audio interface (SAI) modules<br> supporting I2S, AC97, TDM, and | ||
codec/DSP interfaces, including one SAI with 16 Tx and 16 Rx channels, one SAI | codec/DSP interfaces, <br>including one SAI with 16 Tx and 16 Rx channels,<br> one SAI | ||
with 8 Tx and 8 Rx channels | with 8 Tx and 8 Rx channels and <br> three SAI with 2 Tx and 2 Rx channels<br></li><li>One SAI for 8 Tx channels for HDMI output audio<br></li><li>One S/PDIF input for HDMI ARC input</li><br> | ||
< | '''Camera inputs:'''<br><li>Two MIPI-CSI2 camera inputs (4-lane each)</li> | ||
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! scope="row" | Hardware Video Acceleration | ! scope="row" | Hardware Video Acceleration |
Revision as of 15:52, 8 November 2018
Features | i.MX6 Quad / i.MX6 Dual | i.MX8M Dual / i.MX8M QuadLite / i.MX8M Quad |
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CPU | ||
Maximum CPU Frequency | ||
I-Cache/D-Cache | 32 KB/32 KB L1, 1 MB L2 | Arm Cortex-A53: |
External Memory Interface | 2 x 32 LP-DDR2, 1-ch. x 64 DDR3/DDR3L | |
Display Interface | HDMI + PHY, 2 x parallel, 2 x LVDS, MIPI DSI | HDMI Display Interface: support HDCP 2.2 and HDCP 1.4 MIPI-DSI Display Interface: Audio: supporting I2S, AC97, TDM, and codec/DSP interfaces, including one SAI with 16 Tx and 16 Rx channels, one SAI with 8 Tx and 8 Rx channels and three SAI with 2 Tx and 2 Rx channels Camera inputs: |
Hardware Video Acceleration | HD (1080 + 720)p30 video decode HD 1080p30 video encode |
4Kp60 HEVC/H.265 main, and main 10 decoder 4Kp60 VP9 decoder 4Kp30 AVC/H.264 decoder 1080p60 MPEG-2, MPEG-4p2, VC-1, VP8, RV9, AVS, MJPEG, H.263 decoder |
Hardware 2D/3D Graphics Acceleration | HDMI + PHY, 2 x parallel, 2 x LVDS, MIPI DSI | 1.5 GHz |