NXP i.MX95 Technical Guide
 | The NXP i.MX95 Technical Guide documentation from RidgeRun is presently being developed. |
NXP i.MX95 Technical Guide
The i.MX95 applications processor family supports a wide range of edge applications, including automotive connectivity, Industry 4.0, and IoT platforms. This family features six Arm Cortex-A55 cores, an Arm Mali GPU, a 4K VPU, an ISP, ML acceleration via an NPU, and EdgeLock secure enclave security.
RidgeRun is an official member of the NXP registered Partner Program. We created this wiki to support common customers with a single, practical source of documentation, tutorials, and implementation guidance.
Use this guide to move from platform evaluation into board bring-up, system setup, and multimedia validation on NXP i.MX95 hardware. If you need direct support on your project, contact RidgeRun through our Contact Us page.
Image extracted from NXP product page.
RidgeRun understands the value of having a single source of information that shortens time-to-market. This guide brings together hardware preparation, operating system workflows, and media acceleration references so teams can move faster from evaluation to product integration.
Here is a brief feature summary for the NXP i.MX95 platform:
- GPU: Arm Mali G310, 128 GFLOPS
- CPU: Octa-core Armv8.2 at up to 2.0 GHz
- AI Acceleration: 4x eIQ Neutron N3-1024S NPU, 2 TOP/s
- ISP Acceleration: NXP ISP with RGB-IR support
- Encoder Acceleration (H.265): VPU, up to 32 video streams or 1x 4K@60fps
- Camera Support: Up to 8 concurrent cameras, 2.5 Gbps/lane
- Security Acceleration: EdgeLock Secure Enclave and V2X cryptographic accelerator
- Sensors: 1x digital temperature sensor on EVK
- Package Options: Two SoC versions, 15 mm x 15 mm and 19 mm x 19 mm
Explore the guide
The wiki is organized around hardware bring-up, operating system workflows, and multimedia enablement. Use these entry points to jump into the largest sections of the guide.
For additional material, use the table of contents.
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