Capture Subsystem
 | The NXP i.MX95 Technical Guide documentation from RidgeRun is presently being developed. |
Introduction
The capture subsystem on the i.MX95 is responsible for receiving image data from camera inputs and preparing it for use through the Linux video stack. Applications do not interact with the camera hardware directly. Instead, image capture is exposed through the Video4Linux2 (V4L2) framework, which provides the standard interface for opening capture devices, configuring streams, starting and stopping capture, and retrieving image frames.
On i.MX95, the capture path is built around the Image Sensor Interface (ISI) together with the NEO ISP, using MIPI CSI-2 as the external camera input interface.
Capture Subsystem Overview
For i.MX95, image data enters the SoC through the MIPI CSI-2 interface and is then handled by the capture subsystem built around the ISI and NEO ISP. In practice:
- MIPI CSI-2 receives serialized camera data from the sensor
- ISI handles DMA and image formatting tasks
- NEO ISP provides the newer image processing block introduced for i.MX95
Main Capture Components on i.MX95
MIPI CSI-2 Interface
The i.MX95 uses a MIPI CSI-2 camera interface based on Synopsys IP. This is the external high-speed serial interface used to connect supported image sensors to the SoC.
For i.MX95, the MIPI CSI-2 subsystem provides:
- 2 ports
- 4 lanes per port
- Up to 2.5 Gbps per lane
The MIPI CSI-2 host controller is responsible for receiving and decoding the incoming CSI-2 stream. Internally, it is organized into four functional blocks:
- PHY adaptation layer
Handles the D-PHY interface, including low-level PHY management and PHY error handling.
- Packet analyzer
Merges lane data when required, decodes packet headers, and performs error handling such as header checking, correction, frame size error detection, and CRC checking.
- Image data interface
Separates packet header information from image payload data, reorders data into the expected memory layout, and generates the video synchronization signals required downstream. It also performs frame-level and line-level error detection.
- Register bank
Provides configuration and control access through an AMBA APB interface and includes programmable interrupt generation for reporting relevant events to the system.
From a system perspective, the MIPI CSI-2 interface is the front end of the capture subsystem. It receives the sensor stream and passes properly decoded image data into the downstream processing pipeline.
Image Sensor Interface (ISI)
On i.MX95, the ISI is the block that handles DMA and image formatting operations. In the i.MX 9 family, ISI is the main capture-side engine that connects to the available sensor interfaces and manages the movement and formatting of image data inside the SoC.
Common ISI capabilities include:
- Deinterlacing using simple bob and weave methods
- Resizing
- DMA-based controller operation
- Double-buffer synchronization
For i.MX95 specifically, the ISI supports:
- MIPI CSI-2 with 2 ports
- 4 lanes at 2.5 Gbps
- One 4K source at 60 fps with 24 bpp
- Two sources up to 2K at 60 fps with 24 bpp on each channel
- Eight sources up to 2K at 30 fps with 24 bpp on each channel
In other words, on i.MX95 the ISI is not just a simple transport block. It is the central capture engine that performs the memory movement and image formatting needed to feed the rest of the video pipeline.
NEO ISP
The NEO ISP is a dedicated image signal processor introduced with the i.MX95, designed to handle advanced image processing tasks within the capture pipeline.
It operates downstream of the capture interface and complements the ISI by performing processing steps beyond basic data movement and formatting. While the ISI focuses on DMA and image handling, the NEO ISP is responsible for improving image quality and preparing frames for further use in vision and multimedia applications.
The ISP pipeline includes several configurable processing blocks that can be tuned depending on the application. Some representative examples include:
- Automatic White Balance (AWB): Adjusts the color balance of the image based on scene illumination. It uses statistics from the image to estimate the color temperature and applies corrections so that colors appear natural.
- Automatic Gain and Exposure Control (AGC/AEC): Dynamically adjusts sensor gain and exposure time using image statistics (such as histograms) to maintain proper brightness under varying lighting conditions.
- Color Correction Matrix (CCM): Applies a matrix transformation to convert RGB data into a corrected color space (typically YUV), compensating for sensor characteristics and lighting conditions.
Additional ISP blocks support functions such as black level correction, dynamic range compression, lens shading correction, and HDR processing.
The NEO ISP is tightly integrated into the capture subsystem and works together with the ISI and MIPI CSI-2 interface to form a complete camera pipeline on i.MX95. This integration enables efficient processing of high-resolution and high-frame-rate video streams while maintaining image quality.
Capture Capabilities on i.MX95
For i.MX95, the capture subsystem supports high-throughput camera input through MIPI CSI-2 and is designed for multi-stream operation. The main platform capabilities described for this SoC are:
| Feature | i.MX95 |
|---|---|
| Capture controllers | ISI and NEO ISP |
| Camera interface | MIPI CSI-2 using Synopsys |
| Number of CSI-2 ports | 2 |
| Number of lanes per port | 4 |
| Lane speed | 2.5 Gbps |
| Maximum single-source support | 4K at 60 fps, 24 bpp |
| Dual-source support | 2 sources up to 2K at 60 fps, 24 bpp, on each channel |
| Multi-source support | 8 sources up to 2K at 30 fps, 24 bpp, on each channel |
| ISI capabilities | DMA, image formatting, resizing, deinterlacing, double buffering |