Xilinx ZYNQ UltraScale+ Simple Vector Addition with XRT
| Xilinx ZYNQ UltraScale+ MPSoC | ||||
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Introduction
This is an example of hardware acceleration using the FPGA and the Xilinx Runtime Library (XRT). With this workflow, the user can reconfigure the FPGA with a kernel without rebooting the board and allowing applications to run acceleration through FPGA PL kernels. To achieve this, the FPGA manager loads the logic through overlays: loads a device tree overlay configures the FPGA with a target PL and prepares the XRT for communication. Then, the application can execute using the kernel (in the form of PL logic) through the XRT.
XRT, in this case, is implemented as a combination of userspace and kernel driver components. XRT supports both PCIe-based accelerator cards and MPSoC-based platforms and provides a standardized software interface to the FPGA.
