Xilinx ZYNQ UltraScale+ MPSoC/Introduction: Difference between revisions
mNo edit summary |
mNo edit summary |
||
Line 1: | Line 1: | ||
<noinclude> | <noinclude> | ||
{{Xilinx ZYNQ UltraScale+ MPSoC/Head|previous=|next=|metakeywords=}} | {{Xilinx ZYNQ UltraScale+ MPSoC/Head|previous=|next=Introduction/Overview|metakeywords=}} | ||
</noinclude> | </noinclude> | ||
Line 14: | Line 14: | ||
<noinclude> | <noinclude> | ||
{{Xilinx ZYNQ UltraScale+ MPSoC/Foot||}} | {{Xilinx ZYNQ UltraScale+ MPSoC/Foot||Introduction/Overview}} | ||
</noinclude> | </noinclude> |
Revision as of 17:58, 19 October 2023
Xilinx ZYNQ UltraScale+ MPSoC | ||||
---|---|---|---|---|
Introduction | ||||
Getting Started | ||||
Xilinx Kria | ||||
Development | ||||
Development Flows Examples | ||||
GStreamer | ||||
|
||||
Contact Us |
Introduction
This section provides guides on how to get started with the project. In the next wiki pages you can find more information about: