Template:Xilinx ZYNQ UltraScale+ MPSoC/Head: Difference between revisions
mNo edit summary |
mNo edit summary |
||
Line 13: | Line 13: | ||
|fix=Please come back soon to read the completed information on Ridgerun's support for this platform. Please [https://www.ridgerun.com/contact <U>'''Contact'''</U>] RidgeRun OR email to [mailto:support@ridgerun.com <u>'''support@ridgerun.com'''</u>] if you have any questions.''' | |fix=Please come back soon to read the completed information on Ridgerun's support for this platform. Please [https://www.ridgerun.com/contact <U>'''Contact'''</U>] RidgeRun OR email to [mailto:support@ridgerun.com <u>'''support@ridgerun.com'''</u>] if you have any questions.''' | ||
}} | }} | ||
<br> | |||
{| width=100% cellspacing=0 cellpadding=2 style="border: 1px solid black;" class="noprint" | {| width=100% cellspacing=0 cellpadding=2 style="border: 1px solid black;" class="noprint" | ||
| width=33% bgcolor=#ffffe0 | {{#if:{{{previous|}}}|[[Xilinx ZYNQ UltraScale+ MPSoC/{{{previous}}}|Previous: {{{previous}}}]]| }} | | width=33% bgcolor=#ffffe0 | {{#if:{{{previous|}}}|[[Xilinx ZYNQ UltraScale+ MPSoC/{{{previous}}}|Previous: {{{previous}}}]]| }} |
Revision as of 03:27, 30 August 2022
Xilinx ZYNQ UltraScale+ MPSoC documentation is currently under development. |
Xilinx ZYNQ UltraScale+ MPSoC | ||||
---|---|---|---|---|
Introduction | ||||
Getting Started | ||||
Xilinx Kria | ||||
Development | ||||
Development Flows Examples | ||||
GStreamer | ||||
|
||||
Contact Us |