Xilinx ZYNQ UltraScale+ MPSoC/GStreamer/Example Pipelines/Video Decoding: Difference between revisions
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== Network to display == | == Network to display == | ||
We optimized these pipelines to show the low-latency capabilities of this device. | |||
For the sending pipeline please see the [[Xilinx ZYNQ UltraScale+ MPSoC/GStreamer/Example Pipelines/Video Encoding|Video Encoding examples]]. | For the sending pipeline please see the [[Xilinx ZYNQ UltraScale+ MPSoC/GStreamer/Example Pipelines/Video Encoding|Video Encoding examples]]. | ||
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'''H.264''' | '''H.264''' | ||
<syntaxhighlight> | <syntaxhighlight> | ||
gst-launch-1.0 udpsrc port=5000 caps=application/x-rtp,media=video,clock-rate=90000,encoding-name=H264,payload=96 ! rtph264depay ! h264parse ! omxh264dec ! kmssink driver-name=xlnx bus-id=fd4a0000.display fullscreen-overlay=true | gst-launch-1.0 udpsrc port=5000 caps=application/x-rtp,media=video,clock-rate=90000,encoding-name=H264,payload=96 ! rtpjitterbuffer latency=7 ! rtph264depay ! h264parse ! video/x-h264,alignment=nal ! omxh264dec low-latency=true ! fpsdisplaysink text-overlay=false video-sink="kmssink driver-name=xlnx bus-id=fd4a0000.display fullscreen-overlay=true" sync=true -v | ||
</syntaxhighlight> | </syntaxhighlight> | ||
'''H.265''' | '''H.265''' | ||
<syntaxhighlight> | <syntaxhighlight> | ||
gst-launch-1.0 udpsrc port=5000 caps=application/x-rtp,media=video,clock-rate=90000,encoding-name=H265,payload=96 ! rtph265depay ! h265parse ! omxh265dec ! kmssink driver-name=xlnx bus-id=fd4a0000.display fullscreen-overlay=true | gst-launch-1.0 udpsrc port=5000 caps=application/x-rtp,media=video,clock-rate=90000,encoding-name=H265,payload=96 ! rtpjitterbuffer latency=7 ! rtph265depay ! h265parse ! video/x-h265,alignment=nal ! omxh265dec low-latency=true ! fpsdisplaysink text-overlay=false video-sink="kmssink driver-name=xlnx bus-id=fd4a0000.display fullscreen-overlay=true" sync=true -v | ||
</syntaxhighlight> | </syntaxhighlight> | ||
<noinclude>{{Xilinx ZYNQ UltraScale+ MPSoC/Foot|GStreamer/Example Pipelines/Video Encoding|GStreamer/Example Pipelines/Video Transformation}}</noinclude> | <noinclude>{{Xilinx ZYNQ UltraScale+ MPSoC/Foot|GStreamer/Example Pipelines/Video Encoding|GStreamer/Example Pipelines/Video Transformation}}</noinclude> | ||
Revision as of 18:28, 8 December 2022
| Xilinx ZYNQ UltraScale+ MPSoC | ||||
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| Introduction | ||||
| Getting Started | ||||
| Xilinx Kria | ||||
| Development | ||||
| Development Flows Examples | ||||
| GStreamer | ||||
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The following pipelines were tested using the smartcam firmware, which is based on the kv260_ispMipiRx_vcu_DP Vitis platform provided by Xilinx. This platform contains the following input pipeline:
AR1335 camera -> AP1302 ISP -> MIPI CSI-2 RX Subsystem -> Video Frame Buffer Write
Network to display
We optimized these pipelines to show the low-latency capabilities of this device.
For the sending pipeline please see the Video Encoding examples.
H.264
gst-launch-1.0 udpsrc port=5000 caps=application/x-rtp,media=video,clock-rate=90000,encoding-name=H264,payload=96 ! rtpjitterbuffer latency=7 ! rtph264depay ! h264parse ! video/x-h264,alignment=nal ! omxh264dec low-latency=true ! fpsdisplaysink text-overlay=false video-sink="kmssink driver-name=xlnx bus-id=fd4a0000.display fullscreen-overlay=true" sync=true -v
H.265
gst-launch-1.0 udpsrc port=5000 caps=application/x-rtp,media=video,clock-rate=90000,encoding-name=H265,payload=96 ! rtpjitterbuffer latency=7 ! rtph265depay ! h265parse ! video/x-h265,alignment=nal ! omxh265dec low-latency=true ! fpsdisplaysink text-overlay=false video-sink="kmssink driver-name=xlnx bus-id=fd4a0000.display fullscreen-overlay=true" sync=true -v