Template:Xilinx ZYNQ UltraScale+ MPSoC/Head: Difference between revisions
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|title={{{title|Xilinx ZYNQ UltraScale+ MPSoC - {{SUBPAGENAME}}}}} | |title={{{title|Xilinx ZYNQ UltraScale+ MPSoC - {{SUBPAGENAME}}}}} | ||
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|keywords=GStreamer, NVIDIA, Jetson, TX1, TX2, Jetson AGX Xavier, Xavier, AI, Deep Learning, Jetson, TX1, TX2, Jetson TX1, Jetson TX2, Jetson Xavier, NVIDIA Jetson Xavier, NVIDIA Jetson Orin, Jetson Orin, Orin, NVIDIA Orin, NVIDIA Jetson AGX Orin, Jetson AGX Orin, Xilinx, ZYNQ, Xilinx ZYNQ UltraScale+, MPSoC, Xilinx ZYNQ UltraScale+ MPSoC, {{{keywords|}}} | |keywords=GStreamer, NVIDIA, Jetson, TX1, TX2, Jetson AGX Xavier, Xavier, AI, Deep Learning, Jetson, TX1, TX2, Jetson TX1, Jetson TX2, Jetson Xavier, NVIDIA Jetson Xavier, NVIDIA Jetson Orin, Jetson Orin, Orin, NVIDIA Orin, NVIDIA Jetson AGX Orin, Jetson AGX Orin, Xilinx, ZYNQ, Xilinx ZYNQ UltraScale+, MPSoC, Xilinx ZYNQ UltraScale+ MPSoC, UltraScale, UltraScale+, UltraScale MPSoC, {{{keywords|}}} | ||
|description={{{description|Xilinx Zynq® UltraScale+™ MPSoC devices provide 64-bit processor scalability while combining real-time control with soft and hard engines for graphics, video, waveform, and packet processing.}}} | |description={{{description|Xilinx Zynq® UltraScale+™ MPSoC devices provide 64-bit processor scalability while combining real-time control with soft and hard engines for graphics, video, waveform, and packet processing.}}} | ||
}} | }} | ||
Revision as of 11:28, 30 November 2022
 | Xilinx ZYNQ UltraScale+ MPSoC RidgeRun documentation is currently under development. |
| Xilinx ZYNQ UltraScale+ MPSoC | ||||
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| Introduction | ||||
| Getting Started | ||||
| Xilinx Kria | ||||
| Development | ||||
| Development Flows Examples | ||||
| GStreamer | ||||
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