Holoscan Framework/Holoscan Sensor Bridge/Performance: Difference between revisions

Holoscan Framework/Holoscan Sensor Bridge/Performance (view source)

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-This involves configuring the Jetson into a maximum performance mode. With the CUDA ISP in 24-bit colour depth. The latency lowered from 96 to 58 ms by optimizing the pipeline, leading to a 39.5% reduction. By preserving the 64-bit colour colour depth, the latency is still better, leading to 73 ms of glass-to-glass latency.
+This involves configuring the Jetson into a maximum performance mode. With the CUDA ISP in 24-bit colour depth. The latency lowered from 41.61 to 37.93 ms by optimizing the pipeline, leading to a 8.8% reduction.
-More improvement can be applied by offloading the image signal processing to the FPGA, reducing the pressure on the Jetson system. The FPGA can potentially reduce the latency given the dataflow execution pattern offered by FPGA Hardware Acceleration. RidgeRun is exploring new ways to reduce the latency to 50 ms or less for critical applications, optimizing ISP algorithms and using FPGAs.
+More improvement can be applied by offloading the image signal processing to the FPGA, reducing the pressure on the Jetson system. The FPGA can potentially reduce the latency given the dataflow execution pattern offered by FPGA Hardware Acceleration. The minimum latency obtained without altering the FPGA design is 35.96% defining the floor of the latency by just adding a debayer to the image signal processing pipeline.
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