Introduction to Nand Memories

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Abstract

The goal of this page is to provide you the basic concepts that are needed to work with NAND devices as well as useful links that will help you to understand better this kind of technology which is widely used on embedded devices. It is not intended as a comprehensive tutorial but it will provide you a good knowledge on NAND devices, error correction algorithms (ECC) supported on some of the TI platforms; specifically the DM814x and DM816x. The examples use the TI EVM and Z3 boards with the RidgeRun SDK.

The diagrams shown below, and the majority of this information describing NAND devices was drawn from documents created by ELNEC and Micron

Introduction

The NAND flash architecture was introduced by Toshiba in 1989 and it has become the preferred option (over NOR devices) to dominate the non-volatile Flash market due to its features: NAND Flash's high-density, low power, cost effective, and scalable design, among others. All this makes the NAND Flash the ideal choice for multimedia embedded devices. In the following sections you are going to find a brief contrast between the NAND and NOR technologies, followed by a description about the NAND Flash memory array, including the definition of small pages and long page's devices. Also included is a description of the main functions available in a NAND device (read, write, erase, etc). Subsequently a explanation about ECC algorithms to improve the memory reliability is given. The final section of this guide discusses the options provided by TI for the DM816x and DM814x and its uses through the RidgeRun SDK.

References

Differences between NAND and NOR memories

The main difference between NAND and NOR memories are shown in Table 1. The main difference that exists on capacity and performance between both technologies, this makes the NAND ideal for high-capacity storages. Since NOR supports random access, it is widely used for code storage and execution on smaller devices.

Table 1. Differences between NAND and NOR memories
Feature NAND NOR
Capacity ~ 32Gbit ~1Gbit
Access method Sequential Random
Interface I/O interface Full memory interface
Performance Fast read (serial access cycle)
Fast write
Fast erase (approx. 2ms/block)
Fast read (random access)
Slow write
Slow erase (approx. 1s/block)
Life Span 100 000 – 1 000 000 10 000 – 100 000
Price Low High

From a physical point of view, the NAND architecture uses smaller transistors than the NOR devices since it doesn't have to pull down the whole line of data signals. Instead each transistor contains and makes available one bit directly as is shown in Fig. 1. This gives a more efficient architecture to the NAND and reduces the amount of space needed to almost a half of the space needed by each NOR cell, making it simpler to manufacturer.


NAND and OR Cell's architecture
Fig. 1 shows a Single Level Cell architecture (SLC) which holds one bit of information according to its voltage level (1=High, 0=low), however, there is also another kind of architecture called Multi-Level Cell (MLC) which can hold more than two different levels or information bits. In this case, those chips will have a slower transfer speed and also they have a higher power consumption but from the user point of view they have the same functionality. Furthermore, SLC provides better data endurance compared to the same density MLC NAND because of the accuracy required for recognizing the different voltage thresholds (also MLC requires a more sophisticated correction scheme).

Another important difference between the NOR and NAND chips is that the NOR chips are able to guarantee that each of its positions are good positions, i.e, they are fully functional on every single cell from the user point of view and this is because they are built with extra memory cells that are used to "repair" those cells with defects in the memory array. The NOR manufacturing and test process takes care of replacing the bad cells. In case of NAND chips they might contain bad blocks randomly located, some of them are identified during the manufacturing process of the chip while other blocks are damaged during the usage of the NAND chip. For NAND chip support, the software used with the devices needs to have the ability to identify bad blocks as well. Identifying when a block goes bad is done using an ECC algorithms.

Finally, from the user perspective the main difference between these two chips is the interface. The NOR Flash has a full memory-mapped random access interface (like an EPROM) with dedicated address and data lines, however, in the NAND Flash case these lines don't exist, instead they are controlled through commands using addresses and data through a 8/16 bits wide bus (I/O) interface to internal registers.

NAND Flash memory description

The NAND Flash memories can be categorized in Small Page Size and Large Page Size.

The NAND Flash memory consists of blocks, where each block consists of pages, where each page has a "data area" (also called the cell array) and a "Spare Cell Array or Spare Area". Usually one block is composed of 16, 32 or 64 pages. Also each page has 512 bytes in the data area and 16 bytes in the spare area. As total each page has 528 bytes , which is called "Small page". Typically all NAND chips size 1 GB and smaller are small page size devices.

The Large Page Size NAND Flash memories which usually are those larger than 1 GB. A large page size NAND chip contains 2048 bytes of data area and 64 bytes of spare area. The total size in one page is 2112 bytes. Small and large page devices are shown in Fig. 2 and 3, It's important to mention that they contain a set of I/O registers that are sized to match the page size.

Figure 2. Small Page Size Architecture
Figure 3. Large Page Size Architecture


NAND Flash operations are done by blocks or pages according to the operations that will be done. The main three operations are read a page, write a page (program), and a block. Notice reading and writing are done on pages and erasing is done on blocks.

Another possible NAND chip operations or commands include:

Spare Cell Array description

The spare cell array area is used to mark bad blocks discovered during production time or during execution time, and to hold the ECC data. Since the spare cell array is separate from the data area, the spare cell array is often called the Out Of Band (OOB) data.


One of the challanges with NAND is there is not a single standard for the layout of the information stored in the spare area. Fig. 4 shows the spare area data layout recommended by Samsung.

Figure 4. Spare Area distributions according to the page size

Bad block management

NAND Flash devices were designed to serve as a low cost mass storage device. Within its functional specification NAND chips have bad blocks as part of the cost/function trade-off. After manufacturing test, less than 2% of the total blocks are bad. A block is marked as invalid or bad in the case one of the data bits no longer reliably stores data. During normal operation, blocks will be marked based due to the limited number of writes and erase cycles allowed for each NAND device. Bad blocks do not affect the good blocks performance since each block is independent and individually isolated from the bit lines. In order to keep track of which are bad or good blocks in a NAND, the out of band data contains an bad block table.

There are two types of bad blocks:

If you are planning to erase your NAND chip, for instance running a nand scrub command in uboot, it is highly recommended to record the information about the bad blocks before erasing the OOB regions. After entire device is erased, the software will re-identify and mark bad blocks in the memory again. However, the testing done at the factory is more extensive and thus can identify blocks that are less reliable, where in normal operation the device can only identify a block that is unreliable.

There are common ways to handle bad blocks in NAND. Two options are Skip Bad Bloc and Reserved Block Are. The most common method is the skip bad block method which is used by uboot in platforms such as DM816x and DM814x. In embedded devices like the platforms just mentioned you can find an Error Checking and Correction algorithm (ECC) which is used to identify pages with errors (and correct them if is possible). Once a page with a data area is identified, the block is mark as being bad. An ECC code is computed for each page of data and it is stored in the out of band area of each page. These ECC algorithms could be done be software or hardware depending on the hardware support.

Error correction code

NAND Flash memories require an Error Correction Code to ensure the data integrity since the chip is susceptible to data errors. The ECC data is saved in the OOB area of each NAND page.

During the NAND page write operation, the ECC unit (hw or sw) calculates the ECC code based on the data stored in the page. The ECC data is saved in the OOB page area. Subsequently during a read operation the page data is read with its respective ECC code and, then the reverse operation is computed to check that the data is correct. Generally the system is able to correct some amount of errors according to the strength of the algorithm implemented which determines the level of robustness of your storage.

Some of the available ECC algorithms are:

Fig. 5 shows a table provided by Micron with the amount of bits required in spare area by each error correction algorithm according to the level of correction supported.

Figure 5. Amount of required bit for each ECC algorithm

Error correction algorithms supported for DM8148 and DM8168

Platforms based on Texas Instruments SoC processors use a TI defined layout for the Spare Area or OOB data. The position and meaning of the ECC data stored in the OOB data area for each page depends of the algorithm supported or enabled on each platform. All parts of the system must use the same NAND ECC algorithm, including ROM bootloader, user boot loader, uboot-min, uboot and the Linux kernel drivers. For TI DM816x SoC processors, the ROM bootloader uses the BCH8 ECC scheme. For this reason the uboot-min or uboot (depending if you are using DM814x or DM816x) must be flashed into NAND using the same BCH8 ECC algoritm in order to allow the ROM code to load uboot without problems. You can change the ECC algorithm that uboot uses internally, however it must match the algorithm used by the kernel. It is simplist if all components use the same ECC algorithm.

note: You can check the spare area layout in the following file in uboot: src/arch/arm/include/asm/arch-ti81xx/nand.h

Currently the SDK provided by RidgeRun for DM816x and DM814x supports BCH8 by hardware in all its components (uboot, kernel and filesystem) which provides a more robust solution to handle errors in NAND. For more information about ECC computation on DM816x please see page 909 of the TRM

Flashing uboot

  Z3-DM8168-MOD# nandecc hw 2
  HW ECC BCH8 Selected
  Z3-DM8168-MOD# nand write 0x82000000 0x0 0x40000

  NAND write: device 0 offset 0x0, size 0x40000
   262144 bytes written: OK
  Z3-DM8168-MOD# nandecc sw
  SW ECC selected

Ridgerun SDK:
  Z3-DM8168-MOD# nand write 0x82000000 0x0 0x40000

  NAND write: device 0 offset 0x0, size 0x40000
  262144 bytes written: OK

Furthermore the solution provided by RidgeRun has the ability to handle nand chips with 16 bit bus width (like the DM8168-EVM) as well as 8 bit bus width chips (like the DM8168-Z3 board). In both cases the BCH8 ECC algorithm is used.

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