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DrmBgraDisplayOp

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The Holoscan SDK guide is currently under active development. Some sections may be incomplete or change without notice.

Questions? Contact RidgeRun or email to support@ridgerun.com.

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Preliminary reference
This reference is preliminary. The set of available operators and HSDK applications, along with their APIs and documented behavior, may change in future releases.


DrmBgraDisplayOp

DrmBgraDisplayOp presents a CUDA BGRA tensor through an exclusive DRM/KMS output. It is the terminal display operator for Argus and raw Bayer pipelines that already produce BGRA.


DRM/KMS display integration
Contact RidgeRun about your CUDA to DRM/KMS display path. We can assess frame copies and adapt the display operator to your platform.


Input arguments

Argument Default and meaning
width, height Positive dimensions of the BGRA input and display image.
device /dev/dri/card0 by default.
connector_id 0 selects the first suitable connector; a nonzero value requests a specific connector.
mode Empty by default; an explicit mode can be supplied when the automatic selection is not desired.

Ports and data contract

Port Memory Queue Trigger Contract
input CUDA device, contiguous SDK default OnEach U8 rank-3 tensor with shape [height, width, 4] in BGRA order. Terminal display sink with no Holoscan output.
ArgusCameraOp -> DrmBgraDisplayOp
V4L2UserPtrSourceOp -> RawBayerToBgraOp -> DrmBgraDisplayOp

Build

Follow Holoscan RidgeRun Build and Installation for the module build and installation. The operator-specific include, target, and runtime requirements are listed below.

Include drm_bgra_display/drm_bgra_display.hpp and link holoscan::drm_bgra_display. The operator requires CUDA and libdrm on Jetson aarch64.

Example

The output of ArgusCameraOp or RawBayerToBgraOp already has the required BGRA layout:

auto display = graph.op<DrmBgraDisplayOp>(
    "display", width, height, "/dev/dri/card0", 0U, "1920x1080");
graph.add_flow(convert->output, display->input);

The connector and mode are selected during start(). The input dimensions must match the configured display mode. The operator uses two scanout buffers and waits for a page-flip event before reusing the previous buffer, so a slow display can apply backpressure to the terminal stage.

When CUDA DMABUF import is available, the display path can write the scanout buffer without a host staging copy. On Orin, the implementation also supports a CUDA-registered framebuffer mapping and falls back to a mapped host copy when direct import is not available. These paths are implementation details that affect measurements; they do not change the required input contract.


Exclusive display requirements
The process needs access to the DRM device and DRM master ownership. If X11 or another compositor owns the connector, startup or mode selection can fail.


Source reference
You can find the source code at DrmBgraDisplayOp.


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