Kria KV260

FPGA Minutes to Become an Expert
Introduction
What is an FPGA? FPGAs and their applications Popular Vendors Development process When to Choose an FPGA over a GPU/CPU?
FPGA Knowledge
Synthesis Flows High Level Synthesis Vendor Specific Primitives
Xilinx FPGAs
Evaluation boards Minimum Design for KV260 Development workflow and tools Getting Started
Lattice FPGAs
Evaluation boards Development workflow and tools Getting Started
Simulation Tools
CocoTB
AI and Machine Learning
Introduction to AI Architectures and Frameworks Quantisation Pruning
Contact Us

Introduction

Customize an existing capturing overlay

We are going to use the reference platforms repository and the kv260_ispMipiRx_vcu_DP platform as a base. So let's clone the repo and make the xsa project!

git clone https://github.com/Xilinx/kria-vitis-platforms.git -b xlnx_rel_v2022.1
cd kria-vitis-platforms/kv260/platforms/vivado/kv260_ispMipiRx_vcu_DP
make xsa

After the build process completes, lets open the generated output in ./project/kv260_ispMipiRx_vcu_DP.xpr with the vivado GUI.

As a recommendation, since the design is quite big, it might consume al resources, reducing the number of global threads can help with this. Go to Window-> tcl console and input this on the console: set_param general.maxthreads 2

To be able to export the synthesized design we need to convert the project to a hardware project by disabling the vitis extensible platform. Go to Project Manager > Settings and in the General tab uncheck the box, the following image shows the window

Synthesize and generate bitstream

Right click on the block design and press "Validate Design" to make sure there are no errors in the design. Then click on "Generate Bitstream" on the left panel. Depending on your hardware this process will take several minutes.

Export hardware platform

After the bitstream is generated we want to create an "XSA" file which will contain all the files necessary to run the design on the Kria. Click File -> Export -> Export Hardware. On the pop-up window click next, then make sure the radio button "Include bitstream" is selected, press next, then select a path for the file, finally press "Finish".

RidgeRun Services

RidgeRun has expertise in offloading processing algorithms using FPGAs, from Image Signal Processing to AI offloading. Our services include:

• Algorithm Acceleration using FPGAs.
• Image Signal Processing IP Cores.
• Linux Device Drivers.
• Low Power AI Acceleration using FPGAs.
• Accelerated C++ Applications.

And it includes much more. Contact us at https://www.ridgerun.com/contact.