Information for "Xilinx UltraScale Plus VPSS V4L2 Device Tree Binding"
Basic information
| Display title | Xilinx UltraScale Plus VPSS V4L2 Device Tree Binding |
| Default sort key | Xilinx UltraScale Plus VPSS V4L2 Device Tree Binding |
| Page length (in bytes) | 8,543 |
| Namespace ID | 0 |
| Page ID | 1567 |
| Page content language | en - English |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 0 |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | Caguero (talk | contribs) |
| Date of page creation | 23:02, 1 April 2020 |
| Latest editor | Caguero (talk | contribs) |
| Date of latest edit | 23:02, 1 April 2020 |
| Total number of edits | 1 |
| Total number of distinct authors | 1 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |