From RidgeRun Developer Wiki
VPSS Full Fledged Driver
---------------------------
Required properties:
***** General Configuration *****
- compatible: Must be "xlnx,vpss-full".
- reg: Physical base address and length of the registers set for the device.
- clocks: Reference to the video core clock.
- reset-gpios: External GPIO used to reset the IP
- topology: VPSS Topology configured. Possible configurations:
SCALER-ONLY: 0
FULL-FLEDGED: 1
DEINTERLACER-ONLY: 2
CSC_ONLY: 3
VCRESAMPLER-ONLY: 4
HCRESAMPLER-ONLY: 5
- color-depth: Processing precision of the data pipe. Represents the Max-data-width for the components
- pix-per-clock: The pixels per clock property of the IP
- num-vid-components: Number of components used in the VPSS configuration
- max-width: The maximum number of columns supported
- max-height: The maximum number of rows supported
- has-madi: Motion Adaptive Deinterlacer Flag
- framebuf-addr: DDR address for Frame Buffer (required for Deinterlacer and Full Fledged configurations)
***** Components Configuration *****
- sub-ips: This node will contain all the features configured in the VPSS as nodes.
- router: Represent the AXI4-Stream Switch control router configuration:
* addr-offset: The address offset of the component into the VPSS subsystem
* max-num-si: Maximum number of Slaver interfaces
* max-num-mi: Maximum number of Master interfaces
- axis_rst: Represent the Axi Stream reset network configuration:
* addr-offset: The address offset of the component into the VPSS subsystem
* interrupt-present: Are interrupts supported
* isdual: Are 2 channels supported
- aximm_rst:
* addr-offset: The address offset of the component into the VPSS subsystem
* interrupt-present: Are interrupts supported
* isdual: Are 2 channels supported
- hscaler: Represent the Horizontal scaler configuration:
* addr-offset: The address offset of the component into the VPSS subsystem
* phase-shift: Represents the shift needed to get the maximum number of phases (1<<phaseshift)
* num-taps: Number of taps (6 ,8, 10, 12)
* scaler-type: Scaler Algorithm Selected. Possible configurations:
BILINEAR: 0
BICUBIC: 1
POLYPHASE:2
* is422enabled: Color format YUV422 supported
* is420enabled: Color format YUV420 supported
* iscscenabled: Color Space Conversion supported
- vscaler: Represent the Vertical scaler configuration:
* addr-offset: The address offset of the component into the VPSS subsystem
* phase-shift: Represents the shift needed to get the maximum number of phases (1<<phaseshift)
* num-taps: Number of taps (6 ,8, 10, 12)
* scaler-type: Scaler Algorithm Selected. Possible configurations:
BILINEAR: 0
BICUBIC: 1
POLYPHASE:2
* is422enabled: Color format YUV422 supported
* is420enabled: Color format YUV420 supported
* iscscenabled: Color Space Conversion supported
- deinterlacer: Represent the Deinterlacer configuration:
* addr-offset: The address offset of the component into the VPSS subsystem
- letterbox: Represent the Letterbox configuration:
* addr-offset: The address offset of the component into the VPSS subsystem
- csc: Represent the Color Space Converter configuration:
* addr-offset: The address offset of the component into the VPSS subsystem
* is422enabled: Color format YUV422 supported
* isdemowindowenabled: Demo Window supported
- hcresampler: Represent the Horizontal Chroma Resampler configuration:
* addr-offset: The address offset of the component into the VPSS subsystem
* resampling-type: Resampling Method selected
NEAREST-NEIGHBOR: 0
FIXED-COEFFICIENT: 1
FIR: 2
* num-taps: Number of taps (4, 6 ,8, 10)
- vcresampler: Represent the Vertical Chroma Resampler configuration:
* addr-offset: The address offset of the component into the VPSS subsystem
* resampling-type: Resampling Method selected
NEAREST-NEIGHBOR: 0
FIXED-COEFFICIENT: 1
FIR: 2
* num-taps: Number of taps (4, 6 ,8, 10)
- axivdma: Represent the AXI Video DMA configuration:
* addr-offset: The address offset of the component into the VPSS subsystem
* MaxFrameStoreNum: The maximum number of Frame Stores
* HasMm2S: Whether hw build has read channel
* HasMm2SDRE: Read channel supports unaligned transfer
* Mm2SWordLen: Read channel word length
* HasS2Mm: Whether hw build has write channel
* HasS2MmDRE: Write channel supports unaligned transfer
* S2MmWordLen: Write channel word length
* HasSG: Whether hardware has SG engine
* EnableVIDParamRead: Read Enable for video parameters in direct register mode
* UseFsync: DMA operations synchronized to Frame Sync
* FlushonFsync: VDMA Transactions are flushed & channel states reset on Frame Sync
* Mm2SBufDepth: Depth of Read Channel Line Buffer FIFO
* S2MmBufDepth: Depth of Write Channel Line Buffer FIFO
* Mm2SGenLock: Mm2s Gen Lock Mode
* S2MmGenLock: S2Mm Gen Lock Mode
* InternalGenLock: Internal Gen Lock
* S2MmSOF: S2MM Start of Flag Enable
* Mm2SStreamWidth: MM2S TData Width
* S2MmStreamWidth: S2MM TData Width
* Mm2SThresRegEn: MM2S Threshold Register Enable Flag. This corresponds to C_ENABLE_DEBUG_INFO_1
* Mm2SFrmStoreRegEn: MM2S Frame Store Register Enable Flag. This corresponds to C_ENABLE_DEBUG_INFO_5
* Mm2SDlyCntrEn: MM2S Delay Counter (Control Reg) Enable Flag. This corresponds to C_ENABLE_DEBUG_INFO_6
* Mm2SFrmCntrEn: MM2S Frame Counter (Control Reg) Enable Flag. This corresponds to C_ENABLE_DEBUG_INFO_7
* S2MmThresRegEn:S2MM Threshold Register Enable Flag. This corresponds to C_ENABLE_DEBUG_INFO_9
* S2MmFrmStoreRegEn: S2MM Frame Store Register Enable Flag. This corresponds to C_ENABLE_DEBUG_INFO_13
* S2MmDlyCntrEn: S2MM Delay Counter (Control Reg) Enable Flag. This corresponds to C_ENABLE_DEBUG_INFO_14
* S2MmFrmCntrEn: S2MM Frame Counter (Control Reg) Enable Flag. This corresponds to C_ENABLE_DEBUG_INFO_15
* EnableAllDbgFeatures: Enable all Debug features. This corresponds to C_ENABLE_DEBUG_ALL
* AddrWidth: Address Width
Example:
vpss_full_0: vpss_full@a1000000 {
compatible = "xlnx,vpss-full";
reg = <0xa1000000 0x10000>;
clocks = <&vid_stream_clk>;
topology = <1>;
color-depth = <1>; //Represents max-data-width for the subsytems ips
pix-per-clock = <2>;
num-vid-components = <5>;
max-width = <3840>;
max-height = <2160>;
has-madi;
framebuf-addr = <0x20000000>;
sub-ips {
router {
addr-offset= <0x0>;
max-num-si = <10>;
max-num-mi = <10>;
}
axis_rst {
addr-offset= <0x10000>;
interrupt-present;
isdual;
}
aximm_rst {
addr-offset= <0x50000>;
interrupt-present;
isdual;
}
hscaler {
addr-offset= <0x0>;
phase-shift = <6>;
num-taps = <6>;
scaler-type = <1>;
is422enabled;
is420enabled;
iscscenabled;
};
vscaler {
addr-offset= <0x20000>;
phase-shift = <6>;
num-taps = <6>;
scaler-type = <1>;
is420enabled;
};
deinterlacer {
addr-offset = <0x0>;
};
letterbox {
addr-offset = <0x0>;
};
csc {
addr-offset= <0x0>;
is422enabled;
isdemowindowenabled;
};
hcresampler {
addr-offset = <0x0>;
resampling-type = <1>;
num-taps = <4>;
};
vcresampler-in {
addr-offset = <0x0>;
resampling-type = <1>;
num-taps = <4>;
};
vcresampler-out {
addr-offset = <0x0>;
resampling-type = <1>;
num-taps = <4>;
};
axivdma {
addr-offset = <0x0>;
MaxFrameStoreNum = <4>;
HasMm2S;
HasMm2SDRE;
Mm2SWordLen = <128>;
HasS2Mm;
HasS2MmDRE;
S2MmWordLen = <128>;
HasSG;
EnableVIDParamRead;
UseFsync;
FlushonFsync;
Mm2SBufDepth = <512>;
S2MmBufDepth = <512>;
Mm2SGenLock = <1>;
S2MmGenLock = <0>;
InternalGenLock;
S2MmSOF;
Mm2SStreamWidth = <96>;
S2MmStreamWidth = <96>;
Mm2SThresRegEn;
Mm2SFrmStoreRegEn;
Mm2SDlyCntrEn;
Mm2SFrmCntrEn;
S2MmThresRegEn;
S2MmFrmStoreRegEn;
S2MmDlyCntrEn;
S2MmFrmCntrEn;
EnableAllDbgFeatures;
AddrWidth = <32>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
vpss_full0_in: endpoint {
remote-endpoint = <&test_out>;
};
};
port@1 {
reg = <1>;
vpss_full0_out: endpoint {
remote-endpoint = <&test_in>;
};
};
};
};
