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Holoscan Framework/Holoscan Sensor Bridge/Performance: Difference between revisions
Holoscan Framework/Holoscan Sensor Bridge/Performance (view source)
Revision as of 20:09, 3 January 2025
, 3 January→CUDA ISP Results
| Line 81: | Line 81: | ||
| 96 | | 96 | ||
|- | |- | ||
| CUDA ISP | | CUDA ISP (RGB24) | ||
| 3840x2160 (4K) | | 3840x2160 (4K) | ||
| 2.96 (total) 35.6 (core) | | 2.96 (total) 35.6 (core) | ||
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| 35 | | 35 | ||
| 58 | | 58 | ||
- | |||
| CUDA ISP (RGBA64) | |||
| 3840x2160 (4K) | |||
| 3.2 (total) 39.9 (core) | |||
| 448 | |||
| 32 | |||
| 73 | |||
|} | |} | ||
This involves configuring the Jetson into a maximum performance mode. The latency lowered from 96 to 58 ms by optimizing the pipeline, leading to a 39.5% reduction. | This involves configuring the Jetson into a maximum performance mode. With the CUDA ISP in 24-bit colour depth. The latency lowered from 96 to 58 ms by optimizing the pipeline, leading to a 39.5% reduction. By preserving the 64-bit colour colour depth, the latency is still better, leading to 73 ms of glass-to-glass latency. | ||
More improvement can be applied by offloading the image signal processing to the FPGA, reducing the pressure on the Jetson system. The FPGA can potentially reduce the latency given the dataflow execution pattern offered by FPGA Hardware Acceleration. RidgeRun is exploring new ways to reduce the latency to 50 ms or less for critical applications, optimizing ISP algorithms and using FPGAs. | More improvement can be applied by offloading the image signal processing to the FPGA, reducing the pressure on the Jetson system. The FPGA can potentially reduce the latency given the dataflow execution pattern offered by FPGA Hardware Acceleration. RidgeRun is exploring new ways to reduce the latency to 50 ms or less for critical applications, optimizing ISP algorithms and using FPGAs. | ||