PCIe Protocol: Difference between revisions

PCIe Protocol (view source)

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-<seo title="PCIe | PCIe Protocol | RidgeRun Developer" titlemode="replace" metakeywords="PCIe Protocol, PCIe,  PCIe interface, PCIe port, PCIe bus, PCIe standard, PCI 2.2, TLP, Transfer Layer Package, PCI Standard, AGP Standard, PCIe Bus Mastering" metadescription="This wiki page from RidgeRun is about PCIe Protocol"></seo>
+{{#seo:
+|title=PCIe Protocol
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+|description={{{description|This wiki page from RidgeRun is about PCIe Protocol}}}
+}}
 PCIe is a high-speed serial computer expansion bus standard. PCIe was designed as a high-speed replacement for the PCI and AGP standards. The data transmitted is sent over lanes in both directions at the same time, each lane is capable of transfer speeds of around 250 MB/s and each slot can be scaled from 1 to 32 lanes. With 16 lanes, PCIe can support a bandwidth of up to 4 GB/s.