NXP i.MX95 - Introduction - What is i.MX95?-Copy

NXP i.MX95
Introduction
What is i.MX95? Why i.MX95? Why choosing RidgeRun for your i.MX95 software?
Carrier Boards
Toradex i.MX 95 Verdin EVK Overview Boot Devices Audio Switch Yocto Support Setup Yocto Environment Building an Image Flashing the board Getting into the Board Variscite Dart MX95 Overview Boot Devices Yocto Support Setup Yocto Environment Building an Image Flashing the board Getting into the Board
GStreamer Support
How to enable GStreamer Example pipelines Performance
Multimedia Support
Audio Video Capture Capture Interfaces Capture Subsystem Testing Camera Capture Video_Encoding_and_Decoding Streaming RTSP Streaming UDP Streaming GPU Capabilities Examples Performance VPU Capabilities Examples ISP Capabilities How to Enable Examples Video and Image transformations Performance Libcamera Overview GStreamer Cam Test Application
Neural Processing Unit-NPU
eIQ i.MX95 NPU capabilities Machine Learning Software Stack Enabling and testing NPU Evaluating the NPU performance Debugging and analytics tools
Secure Boot
Introduction i.MX95 Secure boot How to enable secure boot
Tools
Arm Performance Studio
Contact Us

This section provides an overview of the i.MX 95 applications processor, highlighting its advanced features in graphics and video processing, machine learning acceleration, and efficient CPU performance. The processor is equipped with robust real-time processing capabilities and enhanced security through the integrated EdgeLock® secure enclave, making it ideal for energy-efficient edge computing. Additionally, it supports a comprehensive array of peripherals and processor cores, ensuring versatility and high performance for a wide range of applications. The figure 1 shows the i.MX 95 Verdin Evaluation Kit.

Fig 1. i.MX 95 SoM. Extracted from link

The i.MX 95 chip integrates a range of advanced hardware units, enhancing its capabilities for various applications. The Central Processing Unit (CPU) comprises six Cortex-A55 cores, one Cortex-M7 core, and 512 kBytes of Cortex-M33 TCM. For graphics processing, it includes an Arm Mali-G310 GPU. Video processing is managed by a dedicated Video Processing Unit (VPU) alongside a JPEG encoder and decoder. Machine learning tasks are accelerated by four eIQ® Neutron N3-1024S Neural Processing Units (NPUs). Additionally, the chip features an Image Signal Processor (ISP) for handling RAW camera images through both streaming and DDR-to-DDR modes. Table 1 summarizes the hardware characteristics of the chip.

Table 1. i.MX 95 Applications Processor Hardware Summary

Feature	Specifications
Arm Cortex-A55 MPCore platform	6 x Arm Cortex-A55 Arm v8.2 fully 64-bit capable L1, L2, and L3 cache with ECC
Arm Cortex-M33 and Cortex-M7 platforms	1 x Arm Cortex-M33, up to 333 MHz frequency 1 x Cortex-M7, up to 800 MHz frequency Arm v8-M supporting Trustzone-M 16 KB + 16 KB (Cortex-M33) and 32 KB + 32 KB (Cortex-M7) caches (ECC) 512 KB (Cortex-M33) + 512 KB (Cortex-M7) TCM or on-chip SRAM (ECC)
Memory	Up to 6.4 GT/s x 32 LPDDR4X/5 (with inline ECC) 3 x uSDHC (SD3.0, SDIO3.0, eMMC5.1) 8 x LPI2C 8 x LPSPI 2 x I3C 1 x Octal SPI, including support for SPI NOR and SPI NAND memories FlexSPI_FLR
Machine learning	High-performance NPU
Graphics	Arm Mali-G310 GPU 3D GPU supporting 50 GFLOPs OpenGL® ES 3.2 Vulkan® 1.2 OpenCL 3.0
Video processors	4Kp30 H.265 and H.264 encode and decode 1 x JPEGENC 1 x JPEGDEC
Display controllers	1 x 350 MHz MIPI-DSI (4-lane, 2.5 Gbps/lane) supporting 4kp30 or 3840 x 1440p60 Up to 1080p60 LVDS Tx (2 x 4-lane or 1 x 8-lane) 16 kByte of SRAM, but it is available for other chip usage when not using for 2D blitter purposes
Camera and ISP	MIPI-CSI and ISP (2 x 4-lane, 2.5 Gbit/s per lane) with PHY (one mux’d with DSI) Up to 1 x 4Kp60 fps (when enabling one MIPI CSI), 2 x 4Kp30, 4 x 1080p60, or 8 x 1080p30 Up to 8 x cameras with MIPI virtual channels
Audio	5 x SAI Audio XCVR PHY 17-lane I2S TDM (32 bit at 768 kHz frequency) Audio XCVR 8-channel MICFIL 2 x MQS
Connectivity	2 x PCIe Gen 3.0 (1-lane) 1 x USB 3.0 Type-C with PHY 1 x USB 2.0 with PHY 2 x 1 Gbit/s Ethernet ports with time sensitive networking (TSN) capabilities 1 x 10 Gbit/s Ethernet port with TSN capabilities IEEE 1588 for sync; and EEE 5 x CAN-FD 2 x 32-pin FLEXIO interfaces (bus or serial I/O)
Low-speed communication peripherals	8 x UART/USART/Profibus
Timers and PWMs	2 x LPIT Four channels Four external trigger sources Generic 32-bit resolution timer Periodical interrupt generation 6 x TPM Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128 16-bit counter, support for free-running counter or modulo counter mode, counting up or down Includes six channels that you configure for input capture, output compare, edge-aligned PWM mode, or center-aligned PWM mode 2 x LPTMR 5 x WDOG 1 x SYS_CTR 2 x TSTMR
GPIO and pin multiplexing	GPIO modules with interrupt capability IOMUXC to provide centralized pad control
Analog	FRO_TUNER 2 x TEMPSENSE 16-channel, 12-bit SAR_ADC 1 x TRGMUX to configure the trigger inputs for various peripherals
Clocking	CCM OSC LPCG
Safety	Integrated functional safety Targeting ISO26262 ASIL-B and IEC61508 SIL2 compliance
Security	TRDC supports up to 16 resource domains Arm TrustZone® (TZ) architecture Secure and trusted access control EdgeLock™ secure enclave Evolved on-die security with run-time attestation, silicon root of trust, trust provisioning, and fine-grain key management augmented by extensive crypto services
System debug	Arm CoreSight® debug and trace architecture TPIU to support off-chip real-time trace Support for 5-pin (JTAG) and SWD debug interfaces
Power management	Support for PMIC integration to supply all power rails Multiple power domains that allow power gating of most digital and analog logic in Low-Power mode GPC: several factors are involved in power management, not just a central controller
Packages	15 x 15 mm FCBGA, 0.5-mm pitch 19 x 19 mm FCBGA, 0.7-mm pitch

Central Processing Unit (CPU)

Cortex A55

The Cortex-A55 is a high efficiency processor with Media Processing Engine (MPE) with NEON technology supporting Advanced Single Instruction Multiple Data architecture.

There are 6 Cortex-A55 cores on this chip.

Cortex-M7

The Arm Cortex-M7 processor is a highly efficient, high-performance, embedded processor that features low interrupt latency, low-cost debug, and has backward compatibility with existing Cortex-M profile processors.

There are 1 Cortex-M7 core on this chip.

Cortex-M33

In this chip, 512 kByte of Cortex-M33 TCM is present.

Graphics Processing Unit (GPU)

The chip has an Arm Mali-G310 and it is the "V2" configuration.

Mali GPU supports OpenGL, OpenGl ES, and Vulkan texture compression APIs.

The main feature of this GPU is to render complex graphics data and performs general purpose processing tasks under the control of the main application processor.

Video Processing Unit (VPU)

In addition to a VPU, the chip contains a JPEG encoder and a JPEG decoder:

• The VPU supports simultaneous encoding or decoding of 32 multiple streams. It features both H.264/AVC and H.265/HEVC encoders and decoders, with maximum throughput of 4K@60fps.

• The JPEG Encoder offers Motion JPEG payload encoding and supports up to 4 simultaneous streams. It achieves up to 400 MSamples/s and conforms to DICOM JPEG standards.

• The JPEG Decoder supports Motion JPEG payload decoding and can handle up to 4 simultaneous streams. It achieves up to 400 MSamples/s.

Neural Processing Unit (NPU)

The chip comes with four eIQ^® Neutron N3-1024S NPU.

The NPU provides efficient processing of machine-learning workloads. It works in conjunction with the chip's CPU to deliver higher performance and lower power consumption for neural network (NN) inference.

This unit natively supports:

• Convolutional neural networks (CNN) including Atrous Separable Convolution networks and Depthwise Separable Convolutional networks, with matrix sizes of:
  • 1x1, 3x3, 5x5, and 7x7, with stride and padding support
  • 1x3, 3x1, 1x5, 5x1, 1x7, and 7x1
• Recurrent Neural networks (RNN), including minimum gated unit (MGU) networks
• Activation function for determining final value of a neuron. Includes support the activation functions: ReLU, ReLUx, HSWISH, Sigmoid, Tanh, eLU, SeLU, LeakyReLU, PReLU and exp(x)
• Sampling or reshaping functions
• Element-wise operations
• Layer operations
• Normalization functions
• Pooling functions
• Fully connected layer output

Image Signal Processor (ISP)

The ISP integrates several functions for handling RAW camera images and supports two modes:

• Streaming mode: Pixel stream is received from one of the two CSI-2 interfaces, and de-bayered pixels are written to DDR via DMAs.
• DDR to DDR mode: The ISP can process more than one camera stream. Processing is frame-based and can support multiple RAW cameras, with DDR as the source of input frames.