NVIDIA Jetson VI Stride Alignment

Overview

The following document gathers together notes about a capture subsystem limitation presented on Jetson platforms and how to deal with it by enabling the "stride alignment" feature.

VI image size limitation

The capture subsystems found on Jetson platforms (Video Input Unit) have a limitation on data acquisition where the bytes per line on the image should be a number divisible by 64.

Bytes per line divisible by 64

VI can capture images where the bytes per line are divisible by 64. Here is an example:

1920x1080 RAW12

bytes: 2
bytes per line: 1920 * 2 = 3840

# Divisible by 64
3840 / 64 = 60

# Total size of the image
1920 * 1080 * 2 = 4147200

Bytes per line Not divisible by 64

For images where the bytes per line are not divisible by 64, the image captured by VI could look kind of corrupted. Here is an example:

4208x3120 RAW10

bytes: 2
bytes per line: 4208 * 2 = 8416

# Not Divisible by 64
8416 / 64 = 131,5

# Total size of the image
4208 * 3120 * 2 = 26257920

Fortunately, there's something we can do to get fix this problem and get the correct image. Check below section

VI Stride alignment

As you can infer, it seems that VI unit needs to handle the data with packets of 64 bytes, but when the number of bytes per line is not a multiple of the packet size value, the image obtained is corrupted. This problem can be fixed if a stride of empty pixels is added to the image to complete the 64 bytes alignment on the frame lines.

Enable Stride alignment

Depending on the Kernel version and platform, the VI driver stride alignment could not enabled. In general, to enabled we need to do the following change in the L4T-Kernel files:

+++ b/kernel/nvidia/include/media/tegra_camera_core.h
@@ -23,7 +23,7 @@
 /* Width alignment */
 #define TEGRA_WIDTH_ALIGNMENT  1
 /* Stride alignment */
-#define TEGRA_STRIDE_ALIGNMENT 1
+#define TEGRA_STRIDE_ALIGNMENT 64
 /* Height alignment */
 #define TEGRA_HEIGHT_ALIGNMENT 1
 /* Size alignment */

In above case we are defining a stride alignment of 64. Check the following example to understand how it works:

4208x3120 RAW10

bytes: 2
bytes per line: 4208 * 2 = 8416

# Not Divisible by 64
8416 / 64 = 131,5

# Stride is added to increase the bytes per line
fixed bytes per line: 132 * 64 = 8448
fixed width: 8448 / 2 = 4224

# Total size of the image
4224 * 3120 * 2 = 26357760

At the end we will get a bigger image which contains the empty pixels at the right, but the image will not be corrupted.

The stride can be increased on multiples of 2 (64, 256, 512, etc), NVIDIA empathises that the worse case would be using 256. Be aware that using 256 can increase the stride depending on the bytes per line value:

1296x1600 RAW10

bytes: 2
bytes per line: 1296 * 2 = 2592

# 64 stride alignment
2592 / 64 = 40,5
fixed bytes per line: 41 * 64 = 2624
fixed width: 2624 / 2 = 1312
image size: 1312 * 1600 * 2 = 4198400

# 64 stride alignment
2592 / 256 = 10,125
fixed bytes per line: 11 * 256 = 2816
fixed width: 2816 / 2 = 1408
image size: 1408 * 1600 * 2 = 4505600

Changes on Stride Alignment

VI2 - TX1/Nano (No tested)

Checking the files, it seems that the stride alignment is selected by TEGRA_SURFACE_ALIGNMENT on kernel/nvidia/include/media/vi2_registers.h (default 64).

VI4 - TX2

For JP-4.2 and older versions, the stride alignment is selected by TEGRA_STRIDE_ALIGNMENT on kernel/nvidia/include/media/tegra_camera_core.h (default 1).
For higher versions than JP-4.2, the stride alignment is selected by RM_SURFACE_ALIGNMENT on kernel/nvidia/drivers/media/platform/tegra/camera/vi/vi4_fops.c (default 256).
Also for higher versions that JP-4.2, bytes per line can be selected as user level, for example:

v4l2-ctl -d /dev/video0 --set-fmt-video=width=1296,height=1600,pixelformat=RG10,bytesperline=3072

VI5 - Xavier

The stride alignment is selected by TEGRA_STRIDE_ALIGNMENT on kernel/nvidia/include/media/tegra_camera_core.h.

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