View source for V4L2 FPGA/Supported Platforms/Zynq MP-SoC

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== Overview ==

Similar to the Zynq-7000 family, the Xilinx Zynq MP-SoC series is a family of FPGA-based SoC that integrates a FPGA and an ARM microprocessor onto the same silicon die. The interconnection of the ARM microprocessor to the several peripherals is often arbitrated by the FPGA configuration, meaning that during the FPGA configuration, is possible to connect or disconnect the ARM microprocessor to the main memory, for example.

The communication between the ARM microprocessor (a.k.a processing system (PS)) and the FPGA (a.k.a programmable logic (PL)) is often through AXI (AMBA variant). To transfer data from one side to another, it is possible to use the cache or the DDR memory as data exchange spaces, achieving bandwidths greater than 4GB/s in the high-performance connections.

One of the advantages of these boards is the possibility of connecting peripherals directly to the FPGA, preprocess the incoming data within the PL, and sending the preprocessed data to the PS ready-to-use.

Additionally, the Zynq MP-SoC is a high-end family and includes more hard cores, allowing these SoCs to communicate to other systems through high-speed networking, PCIe, and others. Also, it is possible to expand the RAM memory, using DDR4 modules.

== Tested platforms ==

=== Zynq Ultrascale+ ZCU106 === 

Evaluation board with a ZCU106 (XCZU7EV) FPGA.

[[File:Ultrascale ZCU106.jpg|200px|Zynq Ultrascale+ ZCU106 Board]]

==== Capabilities ====

CPU specific

* CPU: quad-core Arm® Cortex®-A53 applications processor, dual-core Cortex-R5 real-time processor
* RAM: 4GB DDR4 (soldered) + expandable through SODIMM
* 8 DMA Channels
* PCIe 3.0 x4 lanes

FPGA specific (according to Vivado HLS):

* 504k logic cells
* 230,400 look-up tables (LUT)
* 460,800 flip-flops
* 38 Mb of BRAM organized to 624 units (BRAM 18K)
* 624 DSP slices (Multiplier-Accumulator)


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