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V4L2 FPGA/Supported Platforms/Zynq-7000: Difference between revisions
V4L2 FPGA/Supported Platforms/Zynq-7000 (view source)
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{{V4L2_FPGA/Head|previous=Supported_Platforms/PicoEVB|next=Supported_Platforms/Zynq_MP-SoC}} | {{V4L2_FPGA/Head|previous=Supported_Platforms/PicoEVB|next=Supported_Platforms/Zynq_MP-SoC|metakeywords=Zync 7000, Zync-7000, Artix7, FPGA, Zedboard, ZC7020 FPGA, ZC7020}} | ||
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== Overview == | == Overview == | ||
The Xilinx Zynq-7000 series is a family of FPGA-based SoC that integrates | The Xilinx Zynq-7000 series is a family of FPGA-based SoC that integrates an FPGA (usually a Artix7-based) and an ARM microprocessor onto the same silicon die. The interconnection of the ARM microprocessor to several peripherals is often arbitrated by the FPGA configuration, meaning that during the FPGA configuration, is possible to connect or disconnect the ARM microprocessor to the main memory, for example. | ||
The communication between the ARM microprocessor (a.k.a processing system (PS)) and the FPGA (a.k.a programmable logic (PL)) is often through AXI (AMBA variant). To transfer data from one side to another, it is possible to use the cache or the DDR memory as data exchange spaces, achieving bandwidths greater than 4GB/s in | The communication between the ARM microprocessor (a.k.a processing system (PS)) and the FPGA (a.k.a programmable logic (PL)) is often through AXI (AMBA variant). To transfer data from one side to another, it is possible to use the cache or the DDR memory as data exchange spaces, achieving bandwidths greater than 4GB/s in high-performance connections. | ||
One of the advantages of these boards is the possibility of connecting peripherals directly to the FPGA, | One of the advantages of these boards is the possibility of connecting peripherals directly to the FPGA, preprocessing the incoming data within the PL, and sending the preprocessed data to the PS ready-to-use. | ||
== Tested platforms == | == Tested platforms == | ||
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* 106,400 flip-flops | * 106,400 flip-flops | ||
* 560 kB of BRAM organized to 140 units, each containing 2048 by 18-bit storage | * 560 kB of BRAM organized to 140 units, each containing 2048 by 18-bit storage | ||
* 220 DSP slices (Multiplier-Accumulator) organized | * 220 DSP slices (Multiplier-Accumulator) organized into 18 x 25 | ||
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{{V4L2_FPGA/Foot|Supported_Platforms/PicoEVB|Supported_Platforms/Zynq_MP-SoC}} | {{V4L2_FPGA/Foot|Supported_Platforms/PicoEVB|Supported_Platforms/Zynq_MP-SoC}} | ||
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