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[[File:Ultrascale_ZCU106.jpg|200px|Utrascale+ | [[File:Ultrascale_ZCU106.jpg|200px|Utrascale+]] | ||
| rowspan="3" valign="top" style="text-align:center;" | {{V4L2_FPGA/TOC}} | | rowspan="3" valign="top" style="text-align:center;" | {{V4L2_FPGA/TOC}} | ||
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Additionally, this project provides both drivers and wrappers to adapt your current Image Signal Processing IPs to a V4L2 compliant device. You may be also interested in our ISP library: [[FPGA Image Signal Processor|FPGA ISP]]. | Additionally, this project provides both drivers and wrappers to adapt your current Image Signal Processing IPs to a V4L2 compliant device. You may be also interested in our ISP library: [[FPGA Image Signal Processor|FPGA ISP]]. | ||
[[File:V4l2 fpga sw stack.png|thumb|center|600px | [[File:V4l2 fpga sw stack.png|thumb|center|600px|Figure 1. Software stack description using V4L2 FPGA]] | ||
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