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V4L2 FPGA/Getting the Code/Running the demo: Difference between revisions
V4L2 FPGA/Getting the Code/Running the demo (view source)
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* [[FPGA Image Signal Processor/Modules/HistogramEqualizer|Histogram Equalization]]: a basic histogram equalization from the [[FPGA Image Signal Processor|FPGA ISP]] project | * [[FPGA Image Signal Processor/Modules/HistogramEqualizer|Histogram Equalization]]: a basic histogram equalization from the [[FPGA Image Signal Processor|FPGA ISP]] project | ||
The demo application has two working modes: Command Line Interface (CLI) or web, available in the port <code>5000</code>. The web interface allows | The demo application has two working modes: Command Line Interface (CLI) or web, available in the port <code>5000</code>. The web interface allows changing the dimensions of the image, the GStreamer pattern, and the accelerator. | ||
== Requirements == | == Requirements == | ||