20,290
edits
V4L2 FPGA: Difference between revisions
m
no edit summary
mNo edit summary |
mNo edit summary |
||
| Line 17: | Line 17: | ||
</div> | </div> | ||
| valign="center" style="text-align:center;" | | | valign="center" style="text-align:center;" | | ||
[[File:Ultrascale_ZCU106.jpg|200px|Utrascale+ | [[File:Ultrascale_ZCU106.jpg|200px|Utrascale+]] | ||
| rowspan="3" valign="top" style="text-align:center;" | {{V4L2_FPGA/TOC}} | | rowspan="3" valign="top" style="text-align:center;" | {{V4L2_FPGA/TOC}} | ||
|- | |- | ||
| Line 35: | Line 35: | ||
Additionally, this project provides both drivers and wrappers to adapt your current Image Signal Processing IPs to a V4L2 compliant device. You may be also interested in our ISP library: [[FPGA Image Signal Processor|FPGA ISP]]. | Additionally, this project provides both drivers and wrappers to adapt your current Image Signal Processing IPs to a V4L2 compliant device. You may be also interested in our ISP library: [[FPGA Image Signal Processor|FPGA ISP]]. | ||
[[File:V4l2 fpga sw stack.png|thumb|center|600px | [[File:V4l2 fpga sw stack.png|thumb|center|600px|Figure 1. Software stack description using V4L2 FPGA]] | ||
<br> | <br> | ||
|- | |- | ||