How to change OMX Memory Map
The default amount of memory for OpenMax in a DM816x is 188MB. In some cases, it is not enough, so you need to increase the section of memory reserved for OpenMax which is IPC_SR_FRAME_BUFFERS. In the following link, you can find the EZSDK Memory Map: http://processors.wiki.ti.com/index.php/EZSDK_Memory_Map#Memory_Map_in_the_current_EZSDK_.28version_5.02_onwards.29.
The region IPC_SR_FRAME_BUFFERS is next to the second linux memory region, so the best way to increase it, is to take some of this Linux memory and reassigned to the OMX section.
Increasing OMX memory region
To increase the amount of memory to the region reserved for OpenMax, follow the next steps:
Calculate the new start address for the IPC_SR_FRAME_BUFFERS region
As you can see in the EZSDK Memory Map, the next region after IPC_SR_FRAME_BUFFERS is MC_HDVPSS_NOTIFY_MEM. This region starts at 0xBF900000, so you have to be careful to not overlap it. To avoid overlap it, use the following formula:
base_address = 0xBF900000 – new_size
For example, for a new IPC_SR_FRAME_BUFFERS size of 350MB:
base_address = 0xBF900000 – 0x15E00000 base address = 0xA9B000000
Modify the media controller memory segment configuration
You need to modify the memory segment configuration file for the Media Controller (/board-support/media-controller-utils_3_00_00_05/src/firmware_loader/memsegdef_default.c). The IPC_SR_FRAME_BUFFERS is the Segment 3.
The default values for the Segment 3 are:
/* Segment 3 */
{
1, /* valid */
"IPC_SR_FRAME_BUFFERS", /* name */
0x0BC00000, /* size */
LDR_SEGMENT_TYPE_DYNAMIC_SHARED_HEAP, /* seg_type */
0, /* flags */
0xB3D00000, /* system_addr */
0xB3D00000, /* slave_virtual_addr */
LDR_CORE_ID_A8, /* master_core_id */
(1 << LDR_CORE_ID_VM3) | (1 << LDR_CORE_ID_DM3) | (1 << LDR_CORE_ID_A8) | (1 << LDR_CORE_ID_DSP),
/* core_id_mask */
(1 << LDR_CORE_ID_VM3) | (1 << LDR_CORE_ID_DM3) | (1 << LDR_CORE_ID_DSP), /* cache_enable_mask */
(1 << LDR_CORE_ID_VM3) | (1 << LDR_CORE_ID_DM3) | (1 << LDR_CORE_ID_DSP), /* cache_operation_mask
*/
2 /* shared_region_id */
},
You need to change the size, system addr and the slave virtual_addr values with the new ones in this file. For example, the Segment 3 for a memory size of 350MB is:
/* Segment 3 */
{
1, /* valid */
"IPC_SR_FRAME_BUFFERS", /* name */
0x15E00000, /* size */
LDR_SEGMENT_TYPE_DYNAMIC_SHARED_HEAP, /* seg_type */
0, /* flags */
0xA9B00000, /* system_addr */
0xA9B00000, /* slave_virtual_addr */
LDR_CORE_ID_A8, /* master_core_id */
(1 << LDR_CORE_ID_VM3) | (1 << LDR_CORE_ID_DM3) | (1 << LDR_CORE_ID_A8) | (1 << LDR_CORE_ID_DSP),
/* core_id_mask */
(1 << LDR_CORE_ID_VM3) | (1 << LDR_CORE_ID_DM3) | (1 << LDR_CORE_ID_DSP), /* cache_enable_mask */
(1 << LDR_CORE_ID_VM3) | (1 << LDR_CORE_ID_DM3) | (1 << LDR_CORE_ID_DSP), /* cache_operation_mask
*/
2 /* shared_region_id */
},
You need to modify the Shared Region configuration file for OMX in the ARM (component-sources/omx_05_02_00_48/src/ti/omx/memcfg/memtbl_cfg.h). The IPC_SR_FRAME_BUFFERS region represents the Shared Region 2.
The default configuration for the Shared Region 2 in this file is:
/** * MEMCFG_SRTYPE2, MEMCFG_SRINDEX2, MEMCFG_SRBASE2, MEMCFG_SRSIZE2 * MEMCFG_SRCACHEENABLE2 MEMCFG_SRMEMTYPE2 provide the default values of shared * region2 */ #ifndef MEMCFG_SRTYPE2 #define MEMCFG_SRTYPE2 (MEMCFG_sharedRegionTypeSlave) #endif #ifndef MEMCFG_SRINDEX2 #define MEMCFG_SRINDEX2 ((uint32_t)0x2) #endif #ifndef MEMCFG_SRBASE2 #define MEMCFG_SRBASE2 ((uint32_t)0xB3D00000) #endif #ifndef MEMCFG_SRSIZE2 #define MEMCFG_SRSIZE2 ((uint32_t)0x0BC00000) #endif #ifndef MEMCFG_SRCACHEENABLE2 #define MEMCFG_SRCACHEENABLE2 ((uint32_t)0) #endif #ifndef MEMCFG_SRMEMTYPE2 #define MEMCFG_SRMEMTYPE2 (MEMCFG_sharedRegionMemoryTypeData) #endif
You need to change the MEMCFG_SRBASE2 and MEMCFG_SRSIZE2 with the new values. It is important that this values have to be the same that the values changed in the media controller memory segment configuration file.
For example, the Segment 3 for a memory size of 350MB is:
/** * MEMCFG_SRTYPE2, MEMCFG_SRINDEX2, MEMCFG_SRBASE2, MEMCFG_SRSIZE2 * MEMCFG_SRCACHEENABLE2 MEMCFG_SRMEMTYPE2 provide the default values of shared * region2 */ #ifndef MEMCFG_SRTYPE2 #define MEMCFG_SRTYPE2 (MEMCFG_sharedRegionTypeSlave) #endif #ifndef MEMCFG_SRINDEX2 #define MEMCFG_SRINDEX2 ((uint32_t)0x2) #endif #ifndef MEMCFG_SRBASE2 #define MEMCFG_SRBASE2 ((uint32_t)0xA9B00000) #endif #ifndef MEMCFG_SRSIZE2 #define MEMCFG_SRSIZE2 ((uint32_t)0x15E00000) #endif #ifndef MEMCFG_SRCACHEENABLE2 #define MEMCFG_SRCACHEENABLE2 ((uint32_t)0) #endif #ifndef MEMCFG_SRMEMTYPE2 #define MEMCFG_SRMEMTYPE2 (MEMCFG_sharedRegionMemoryTypeData) #endif
Kernel bootargs
If you increase the OMX memory region, you need to decrease the second memory region or not to load it. Follow the next steps to do it:
cd $DEVDIR
make config
- Kernel configuration
- *** Extra parameters to pass to kernel boot args ***
The first linux region in the extra parameters to pass to kernel bootargs is: mem=364M@0x80000000.
The second linux region is: mem=320M@0x9FC00000
This second linux region needs to be deleted or reduced for the kernel bootargs in order to not overlap the OMX region.
Rebuild the DSP firmware
The DSP firmware needs to be rebuild in order to have the same memory map. To rebuild it, follow this guide Rebuild DSP firmware
Rebuild the EZSDK
Follow the next steps:
cd $DEVDIR/proprietary/ezsdk-5_05_02_00 make clean make make install
To check the OMX memory size in the target, use sys_top tool.