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V4L2 FPGA/Examples/Convolutioner: Difference between revisions
V4L2 FPGA/Examples/Convolutioner (view source)
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For these measurements, we are using a 3x3 kernel. It is completely possible to have greater kernels without sacrificing speed, thanks to parallelism in terms of pixel calculation, which actually lasts one clock. Besides, having greater kernels will lead to more area consumption. | For these measurements, we are using a 3x3 kernel. It is completely possible to have greater kernels without sacrificing speed, thanks to parallelism in terms of pixel calculation, which actually lasts one clock. Besides, having greater kernels will lead to more area consumption. | ||
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|issue='''Convolution accelerator is still under development. The current frame rate is limited due to the PCI-e 2.0, where the PicoEVB only uses one communication lane.''' | |||
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<center>'''Do you need us to enhance this or building more complex accelerators?'''</center> | <center>'''Do you need us to enhance this or building more complex accelerators?'''</center> | ||
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<center> | <center> | ||
[[File:RR Contact Us.png|200px|link=http://www.ridgerun.com/contact]] | [[File:RR Contact Us.png|200px|link=http://www.ridgerun.com/contact]] | ||