How to: Create basic bitstream and first stage bootloader for the ZedBoard SDK: Difference between revisions
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4. Select the project folder and the "AXI System Interconnect Type" as shown in the figure: | 4. Select the project folder and the "AXI System Interconnect Type" as shown in the figure and click next: | ||
[[Image:xps-new-project.jpg|center|600px|xps-new-project.jpg]] | [[Image:xps-new-project.jpg|center|600px|xps-new-project.jpg]] | ||
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5. Select the "Avnet" vendor and the "ZedBoard" board, then click next: | |||
[[Image:xps-board-selection.jpg|center|600px|xps-board-selection.jpg]] | |||
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[[Category:Zynq7000]] | [[Category:Zynq7000]] |
Revision as of 19:14, 5 February 2015
Introduction
This guide will help the user to understand the methods that need to be done in order to create a basic bitstream and a first stage bootloader for the ZedBoard. Included in the RidgeRun SDK there are default files for this components, but this wiki will serve as a tutorial for creating new ones.
Steps
1. Make sure you have installed the Xilinx tools. For reference check the following:
Ubuntu 12.04 useful installation hints.
2. Open Xilinx Platform Studio:
xps
3. Select "Create new project using Base System Builder".
4. Select the project folder and the "AXI System Interconnect Type" as shown in the figure and click next:
5. Select the "Avnet" vendor and the "ZedBoard" board, then click next: